UPD448012GY-B70X-MJH Renesas Electronics America, UPD448012GY-B70X-MJH Datasheet

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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

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EXTENDED TEMPERATURE OPERATION Description μ The PD448012 high speed, low power, 8,388,608 bits (524,288 words by 16 bits) CMOS static RAM. μ The PD448012-X has two chip enable pins (/CE1, CE2) to extend the capacity. μ The PD448012-X ...

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Ordering Information Part number μ PD448012GY-B55X-MJH 48-pin PLASTIC TSOP (I) μ PD448012GY-B70X-MJH (12x18) (Normal bent) μ PD448012GY-B85X-MJH μ PD448012GY-B10X-MJH μ PD448012GY-C70X-MJH μ PD448012GY-C85X-MJH μ PD448012GY-C10X-MJH μ PD448012GY-C12X-MJH μ PD448012GY-B55X-MJH-A μ PD448012GY-B70X-MJH-A μ PD448012GY-B85X-MJH-A μ PD448012GY-B10X-MJH-A μ PD448012GY-C70X-MJH-A μ PD448012GY-C85X-MJH-A μ ...

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Pin Configuration (Marking Side) /xxx indicates active low signal. 48-pin PLASTIC TSOP (I) (12x18) (Normal bent) A15 1 A14 2 A13 3 A12 4 A11 5 A10 /WE 11 CE2 12 ...

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Block Diagram V CC GND A0 Address buffer A18 I/O1 - I/O8 I/O9 - I/O16 /CE1 CE2 /LB /UB /WE /OE Truth Table /CE1 CE2 /OE /WE /LB H × × × × × L × × × ...

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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage V CC Input / Output voltage V Operating ambient temperature T Storage temperature T stg Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above ...

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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2) Parameter Symbol Input leakage current I/O leakage current I/O CE2 = V Operating supply ...

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DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2) Parameter Symbol Input leakage current I/O leakage current I/O CE2 = V Operating supply ...

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AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions μ μ [ PD448012-B55X, PD448012-B70X, Input Waveform (Rise and Fall Time ≤ 5 ns Output Waveform V Output Load 1TTL + 50 ...

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Read Cycle (1/2) (B version) Parameter Symbol Read cycle time t Address access time t /CE1 access time t CO1 CE2 access time t CO2 /OE to output valid t /LB, /UB to output valid t Output hold from address ...

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Read Cycle Timing Chart Address (Input) /CE1 (Input) CE2 (Input) /OE (Input) /LB, /UB (Input) I/O (Output) Remark In read cycle, /WE should be fixed to high level CO1 t LZ1 t CO2 t ...

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Write Cycle (1/2) (B version) Parameter Symbol Write cycle time t WC /CE1 to end of write t CW1 CE2 to end of write t CW2 /LB, /UB to end of write t Address valid to end of write t ...

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Write Cycle Timing Chart 1 (/WE Controlled) Address (Input) /CE1 (Input) CE2 (Input /WE (Input) /LB, /UB (Input) I/O (Input / Output) Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE ...

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Write Cycle Timing Chart 2 (/CE1 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated ...

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Write Cycle Timing Chart 3 (CE2 Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated ...

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Write Cycle Timing Chart 4 (/LB, /UB Controlled) Address (Input) /CE1 (Input) CE2 (Input) /WE (Input) /LB, /UB (Input) High impedance I/O (Input) Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. ...

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Low V Data Retention Characteristics (T CC Parameter Symbol Test Condition /CE1 ≥ V − 0.2 V, CE2 ≥ V Data retention V CCDR1 CC supply voltage V CE2 ≤ 0.2 V CCDR2 /LB = /UB ≥ CCDR3 ...

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Data Retention Timing Chart (1) /CE1 Controlled t CDR V CC Note V (MIN.) CC /CE1 V (MIN (MIN.) CCDR V (MAX.) IL GND Note B version : 2 version : 2.2 V Remark On the ...

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Controlled t CDR V CC Note V (MIN.) CC /LB, /UB V (MIN (MIN.) CCDR V (MAX.) IL GND Note B version : 2 version : 2.2 V Remark On the data retention ...

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Package Drawing 48-PIN PLASTIC TSOP(I) (12x18 NOTES 1. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 ...

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Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the Types of Surface Mount Device μ PD448012GY-BxxX-MJH μ PD448012GY-CxxX-MJH μ PD448012GY-BxxX-MJH-A μ PD448012GY-CxxX-MJH-A <R> Quality Grade • A quality grade of the products is “Standard”. • ...

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Revision History Edition/ Page Type of Date This Previous revision edition edition 7th edition/ p.20 p.20 Addition Sep. 2006 Location (Previous edition → This edition) Quality Grade Section of Quality Grade has been added. Data Sheet M14466EJ7V0DS μ PD448012-X Description ...

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MEMO ] 22 Data Sheet M14466EJ7V0DS μ PD448012-X ...

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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

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The information in this document is current as of September, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most ...