AM29F016B-90EC AMD (ADVANCED MICRO DEVICES), AM29F016B-90EC Datasheet - Page 12

• Manufacturer Part Number: AM29F016B-90EC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F016B-90EC

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 40mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

the Temporary Sector Group Unprotect diagram (Fig-
ure 16) shows the timing waveforms, for this feature.
12
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
Figure 1. Temporary Sector Group Unprotect
once again.
Sector Group Unprotect
Program Operations
Completed (Note 2)
Operation
Perform Erase or
RESET# = V
RESET# = V
Temporary
(Note 1)
START
ID
IH
21444D-8
Am29F016B
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
IL
or WE# = V
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
, the device does not ac-
IH
. To initiate a write cy-
IH
during power up, the
CC
power-up and
LKO
.
CC
CC