CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 33

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Table 7. Line Interface Timing Parameter Values (continued)
Table 8. OIF-SPI Level 3 Transmit System Interface Timing Parameter Values
Table 9. OIF-SPI Level 3 Receive System Interface Timing Parameter Values
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
Notes:
23. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4V point of the input to the 1.4V point of
24. When a hold time is specified between an input and a clock, the hold time is the time in the nanoseconds from the 1.4V point of the clock to the 1.4V point of
25. Output propagation delay time is the in nanoseconds from the 1.4V point of the reference signal to the 1.4V point of the output.
26. Maximum output propagation delays are measured with 30-pF load on the inputs.
RXCLKF
RXDS
RXDH
RXFPS
RXFPH
PARINS
PARINH
TFCLK
TFCLKD
TENBS
TENBH
TDATS
TDATH
TPRTYS
TPRTYH
TSOPS
TSOPH
TEOPS
TEOPH
TERRS
TERRH
TSXS
TSXH
TMODS
TMODH
PTADRS
PTADRH
DTPAO
STPAO
PTCAO
RFCLK
RFCLKD
RENBS
RENBH
RDATD
RPRTYD
Parameter
Parameter
Parameter
the clock.
the input.
[21]
[21]
[21]
[22]
[21]
RXCLK Fall Time
Recovered Data Set-up to ↑ of RXCLK
Recovered Data Hold from ↑ of RXCLK
RXFRAME_PULSE Set-up to ↑ of RXCLK
RXFRAME_PULSE Hold from ↑ of RXCLK
SONETRX_PARIN Set-up to ↑ of RXCLK
SONETRX_PARIN Hold from ↑ of RXCLK
TFCLK Frequency
TFCLK Duty Cycle
TENB Set-up time to TFCLK
TENB Hold time to TFCLK
TDAT[31:0] Set-up time to TFCLK
TDAT[31:0] Hold time to TFCLK
TPRTY Set-up time to TFCLK
TPRTY Hold time to TFCLK
TSOP Set-up time to TFCLK
TSOP Hold time to TFCLK
TEOP Set-up time to TFCLK
TEOP Hold time to TFCLK
TERR Set-up time to TFCLK
TERR Hold time to TFCLK
TSX Set-up time to TFCLK
TSX Hold time to TFCLK
TMOD Set-up time to TFCLK
TMOD Hold time to TFCLK
PTADR Set-up time to TFCLK
PTADR Hold time to TFCLK
TFCLK HIGH to DTPA Valid
TFCLK HIGH to STPA Valid
TFCLK HIGH to PTCA Valid
RFCLK Frequency
RFCLK Duty Cycle
RENB Set-up time to RFCLK
RENB Hold time to RFCLK
RFCLK HIGH to RDAT[31:0] Valid
RFCLK HIGH to RPRTY Valid
Description
[24]
Description
[24]
[24]
[24]
[24]
[23]
[24]
Description
[24]
[24]
[25, 26]
[24]
[25, 26]
[25, 26]
[23]
[23]
[23]
[23]
[23]
[23]
[23]
[23]
[25, 26]
CONFIDENTIAL
[24]
[23]
[25, 26]
Min.
Min.
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
1.5
1.5
40
40
2
2
2
2
2
2
2
2
2
–
2
Min.
1.25
1.25
1.25
1.5
1.5
1.5
–
Max.
Max.
104
104
60
60
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
6
6
–
–
6
6
CY7C9536B
Max.
1.5
–
–
–
–
–
–
Page 33 of 46
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
Unit
ns
ns
ns
ns
ns
ns
ns