CY7C09569V-67AC Cypress Semiconductor Corp, CY7C09569V-67AC Datasheet - Page 6

• Manufacturer Part Number: CY7C09569V-67AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-67AC

• Density: 576Kb
• Access Time (max): 20ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 340mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / Rohs Status: Not Compliant

Selection Guide
Pin Definitions
Document Number: 38-06054 Rev. *D
f
Max. Access Time (Clock to Data, Pipelined)
Typical Operating Current I
Typical Standby Current for I
Typical Standby Current for I
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
B
V
V
MAX2
0L
0L
SS
DD
Left Port
0L
L
L
–A
–B
L
L
L
–I/O
(Pipelined)
13/14L
3L
L
L
L
35L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
OE
R/W
FT/PIPE
BM, SIZE
BE
Right Port
0R
R
0R
R
–A
R
R
R
–I/O
13/14R
R
R
35R
R
CC
SB3
SB1
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins. To load this address into
the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST
is asserted LOW
Chip Enable Input.
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output.
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Byte Select Inputs. Asserting these signals enable read and write operations to the corre-
sponding bytes of the memory array.
Select Pins for Bus Matching. See Bus Matching for details.
Big Endian Pin. See Bus Matching for details.
Ground Input.
Power Input.
(Both Ports CMOS Level)
(Both Ports TTL Level)
0
–A
13
for 16K, A
CY7C09579V
–100
100
250
30
10
5
0
–A
14
Description
for 32K devices).
CY7C09579V
–83
240
83
25
10
6
CY7C09579V
–67
230
67
25
10
8
CY7C09569V
CY7C09579V
Unit
MHz
mA
mA
ns
A
MAX
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