CY62128BLL-70ZRI Cypress Semiconductor Corp, CY62128BLL-70ZRI Datasheet
CY62128BLL-70ZRI
Manufacturer Part Number
CY62128BLL-70ZRI
Description
Manufacturer
Cypress Semiconductor Corp
Specifications of CY62128BLL-70ZRI
Density
1Mb
Access Time (max)
70ns
Operating Supply Voltage (typ)
5V
Package Type
TSOP
Operating Temp Range
-40C to 85C
Supply Current
15mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Word Size
8b
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY62128BLL-70ZRI
Manufacturer:
CYPRESS
Quantity:
191
28B MoBL
®
Features
Functional Description
The CY62128B is a high-performance CMOS static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE
HIGH Chip Enable (CE
and three-state drivers. This device has an automatic
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. **
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
• Low standby power (70 ns, LL version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
CE 1
CE 2
WE
Logic Block Diagram
OE
— 82.5 mW (max.) (15 mA)
— 110 W (max.) (15 A)
V
A
CE
WE
A
A
A
A
A
NC
CC
A
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
A
A
A
16
A
A
12
14
15
13
11
7
4
5
6
2
8
9
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(not to scale)
Reverse TSOP I
INPUT BUFFER
Top View
512x 256x 8
DECODER
COLUMN
ARRAY
2
), an active LOW Output Enable (OE),
POWER
DOWN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
, CE
A
A
A
A
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
CE
A
OE
3
2
1
0
10
0
1
2
3
4
5
6
7
1
2
•
CE
V
, and OE options
A
A
WE
A
A
A
A
NC
A
A
CC
A
A
A
A
11
13
15
16
14
12
9
8
2
7
6
5
4
3901 North First Street
1
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
), an active
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
(not to scale)
Top View
STSOP
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
able Two (CE
through I/O
address pins (A
Reading from the device is accomplished by taking Chip En-
able One (CE
Write Enable (WE) and Chip Enable Two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
•
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
1
9
) and Write Enable (WE) inputs LOW and Chip En-
Pin Configurations
7
San Jose
2
) is then written into the location specified on the
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
0
1
2
3
2
LOW), the outputs are disabled (OE HIGH), or
1
7
6
5
4
3
2
1
0
1
G g
) input HIGH. Data on the eight I/O pins (I/O
I/O 0
I/O 1
I/O 2
) and Output Enable (OE) LOW while forcing
gnc
G ND
A 16
A 14
A 12
NC
GN
0
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
through A
Top View
CE
V
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
A
A
A
A
A
NC
A
A
CC
A
A
A
A
128K x 8 Static RAM
11
13
15
16
14
12
SOIC
9
8
2
7
6
5
4
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
CY62128B MoBL
CA 95134
LOW, CE
).
CE 2
A 10
CE 1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
V
A 15
WE
A 13
A 8
A 9
A 11
OE
CC
0
through I/O
(not to scale)
Top View
TSOP I
Revised June 19, 2002
2
HIGH, and WE LOW).
•
7
) are placed in a
2
) HIGH. Under
408-943-2600
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
25
OE
A
CE
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
0
1
2
3
6
7
6
5
4
3
2
1
0
1
®
0
1
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