CY62157DV18LL-55BVI Cypress Semiconductor Corp, CY62157DV18LL-55BVI Datasheet - Page 5
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CY62157DV18LL-55BVI
Manufacturer Part Number
CY62157DV18LL-55BVI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY62157DV18LL-55BVI.pdf
(10 pages)
Specifications of CY62157DV18LL-55BVI
Density
8Mb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
1.8V
Address Bus
19b
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
20mA
Operating Supply Voltage (min)
1.65V
Operating Supply Voltage (max)
1.95V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
16b
Number Of Words
512K
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY62157DV18LL-55BVI
Manufacturer:
CY
Quantity:
80
Company:
Part Number:
CY62157DV18LL-55BVI
Manufacturer:
CYPRESS
Quantity:
173
Switching Characteristics
Switching Waveforms
Document #: 38-05126 Rev. *B
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
DATA OUT
ADDRESS
Read Cycle No. 1 (Address Transition Controlled)
Notes:
10. At any given temperature and voltage condition, t
12. t
13. The internal Write time of the memory is defined by the overlap of WE, CE
14. Device is continuously selected. OE, CE
15. WE is HIGH for Read cycle.
11. If both byte enables are toggled together, this value is 10 ns.
9.
Parameter
[11]
Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
the specified I
HZOE
, t
HZCE
[13]
, t
OL
HZBE
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High-Z
Write Cycle Time
CE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
, and t
1
1
1
1
1
1
PREVIOUS DATA VALID
LOW or CE
LOW or CE
HIGH or CE
LOW or CE
HIGH or CE
LOW or CE
HZWE
transitions are measured when the outputs enter a high-impedance state.
Description
(Over the Operating Range)
2
2
2
2
2
2
HIGH to Data Valid
HIGH to Low Z
HIGH to Power-up
HIGH to Write End
[10]
1
LOW to High Z
LOW to Power-down
[10, 12]
[10, 12]
[10]
= V
t
IL
OHA
, BHE and/or BLE = V
[10]
HZCE
[10, 12]
is less than t
t
AA
[10]
[10, 12]
[14, 15]
LZCE
IL
, CE
, t
[9]
HZBE
1
2
= V
= V
CY62157DV18-55
Min.
t
RC
is less than t
IL
55
10
10
55
45
45
45
45
25
10
IH
5
0
5
0
0
0
, BHE and/or BLE = V
.
CC(typ.)/2
LZBE
Max.
55
55
25
20
20
55
55
20
20
, input pulse levels of 0 to V
, t
HZOE
IL
is less than t.
.
CY62157DV18-70
Min.
70
10
10
70
60
60
50
60
30
10
5
0
5
0
0
0
DATA VALID
CC(typ.)
Max.
70
70
35
25
25
70
70
25
25
CY62157DV18
, and output loading of
MoBL2
Page 5 of 10
Unit
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ns
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ns
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ns
ns
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ns
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