CY7C1329G-133AC Cypress Semiconductor Corp, CY7C1329G-133AC Datasheet
CY7C1329G-133AC
Specifications of CY7C1329G-133AC
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CY7C1329G-133AC Summary of contents
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... Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode Option Functional Description [1] The CY7C1329G SRAM integrates 65,536 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Logic Block Diagram A0, A1, A ADDRESS REGISTER ...
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... V 10 SSQ V 11 DDQ DDQ V 21 SSQ BYTE SSQ V 27 DDQ Document #: 38-05393 Rev. *A 166 MHz 3.5 240 100-pin TQFP CY7C1329G CY7C1329G 133 MHz Unit 4.0 ns 225 DDQ SSQ B BYTE SSQ DDQ DDQ SSQ A A BYTE SSQ DDQ A A Page [+] Feedback ...
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... CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a three-state condition. CY7C1329G , ...
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... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
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... L None None External External External External External Next Next Next Next Next Next Current Current Current Current Current BWE ,BW ,BW ,BW ) and BWE = WRITE = H when all Byte Write Enable signals CY7C1329G WRITE ADSP ADSC ADV Writes may occur only on subsequent clocks [A:D] ...
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... Truth Table for Read/Write (continued) Function Write Bytes D, B Write Bytes Write Bytes D, C Write Bytes Write Bytes Write All Bytes Write All Bytes Document #: 38-05393 Rev BWE CY7C1329G Page [+] Feedback ...
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... Max, Device Deselected, All speeds DD ≥ V ≤ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1329G Ambient Temperature DDQ 0°C to +70°C 3.3V 2.5V –5% –5%/+10% to +5% Min. Max. Unit 3.135 3.6 V 2.375 2.625 V 2 ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1329G TQFP Package Unit °C/W 41.83 °C/W 9.99 Test Conditions Max. Unit ...
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... Document #: 38-05393 Rev. *A [11, 12] 166 MHz Description Min. 1.5 Set-up before CLK Rise 1.5 [A:D] 1.5 1.5 0.5 0.5 0.5 0.5 Hold after CLK Rise [A:D] 0.5 0.5 CY7C1329G 133 MHz Max Min. Max Unit 1.5 ns 1.5 ns 1.5 ns 1.5 ns 0.5 ns 0 ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1329G A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05393 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW CY7C1329G ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 ...
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... The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 20 HIGH. Document #: 38-05393 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1329G A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1329G-133AC 166 CY7C1329G-166AC Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05393 Rev. *A High-Z DON’ ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1329G 51-85050-*A ...
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... Document History Page Document Title: CY7C1329G 2-Mb (64K x 32) Pipelined Sync SRAM Document Number: 38-05393 REV. ECN NO. Issue Date ** 200661 See ECN *A 213342 See ECN Document #: 38-05393 Rev. *A Orig. of Change Description of Change NJY New Data Sheet VBL Updated Ordering Info section: added -166AC ...