CY7C1339B-133AI Cypress Semiconductor Corp, CY7C1339B-133AI Datasheet
CY7C1339B-133AI
Specifications of CY7C1339B-133AI
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CY7C1339B-133AI Summary of contents
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... ZZ Cypress Semiconductor Corporation Document #: 38-05141 Rev. *A The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when V All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock ...
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... DQ BYTE2 SSQ V DDQ DDQ V SSQ BYTE3 SSQ V DDQ Document #: 38-05141 Rev. *A 7C1339B-166 7C1339B-133 3.5 4.0 420 375 100-pin TQFP 14 15 CY7C1339B CY7C1339B 7C1339B-100 Unit 5.5 ns 325 DDQ V 76 SSQ BYTE1 SSQ V 70 DDQ DDQ 60 V SSQ BYTE0 SSQ V 54 DDQ ...
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... Pin Configurations (continued Document #: 38-05141 Rev. *A 119-ball BGA CY7C1339B (128K × 32 ADSP DDQ ADSC DDQ ADV DDQ CLK BWE DDQ MODE DNU DNU DNU DDQ CY7C1339B DDQ DDQ DDQ DDQ DNU NC V DDQ Page ...
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... When ADSP and [1:0] are also loaded into the burst counter. When ADSP and [1:0] during the previous clock rise of the Read cycle. The direction of the pins is controlled CY7C1339B , CE , and CE are sampled active and BWE). ...
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... Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1339B is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQ drivers safety precaution, DQ three-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... The device must be deselected prior to entering the “sleep” mode remain inactive for the duration returns LOW. Description Test Conditions ZZ > > < 0. ADSP CY7C1339B , ADSP, and ADSC must after the ZZ input ZZREC Min. Max. – 0. – 0. CYC 2t CYC ADSC ADV ...
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... OE is asynchronous and is not sampled with the clock rise masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05141 Rev BWE [3:0]. CY7C1339B Writes may occur only on subsequent clocks ...
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... IN IN DDQ 7.5-ns cycle, 133 MHz 1/t MAX CYC 10-ns cycle, 100 MHz Max Device Deselected, DD ≥ V ≤ CY7C1339B Ambient [8] Temperature 2.5V −5% 0°C to +70°C 3.3V −5%/+10% 3.3V /+10% –40°C to +85°C Min. Max. 3.135 3.6 2.375 3.6 2.4 2.0 ...
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... MHz 3. 3.3V DDQ R= 317/1667 Ω 3.3/2.5V OUTPUT 351/1538 Ω DDQ DDQ INCLUDING JIG AND (b) SCOPE Test Conditions Symbol CY7C1339B TQFP Max. BGA Max [10] ALL INPUT PULSES 3.0/2.5V 90% 10% GND ≤ 1V/ns (c) TQFP Typ. BGA 41.83 47.63 9.99 11.71 Unit pF ...
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... Shown in (a) and ( test loads diagram less than t and t is less than t EOHZ EOLZ CHZ CLZ CY7C1339B -133 -100 Max. Min. Max. Min. 7.5 10 1.9 3.5 1.9 3.5 1.5 1.5 0.5 0.5 3.5 4 ...
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... WDx stands for Write Data to Address X. Document #: 38-05141 Rev. *A Burst Write ADSP ignored with CE CL WD2 masks ADSP UNDEFINED = DON’T CARE , and GW to define a Write cycle (see Write Cycle Descriptions table). CY7C1339B Pipelined Write Unselected inactive 1 ADSC initiated Write WD3 Unselected with CE 2 High Page ...
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... RDx stands for Read Data from Address X. Document #: 38-05141 Rev. *A Burst Read ADSP ignored with Suspend Burst ADH RD2 OEHZ t DOH CLZ = DON’T CARE = UNDEFINED CY7C1339B Unselected Pipelined Read inactive 1 ADSC initiated Read RD3 masks ADSP Unselected with CHZ 2 Page ...
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... Data bus is driven by SRAM, but data is not guaranteed. Document #: 38-05141 Rev. *A Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP OEHZ t DS See Note Out Out In = DON’T CARE = UNDEFINED CY7C1339B Unselected Pipelined Read inactive DOH Out Out Out Out t CHZ Page ...
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... LOW CE 2 HIGH I/Os Notes: 18. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 19. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05141 Rev ZZS I (active DDZZ Three-state Three-state CY7C1339B t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 166 CY7C1339B-166AC CY7C1339B-166BGC 133 CY7C1339B-133AC CY7C1339B-133BGC CY7C1339B-133AI CY7C1339B-133BGI 100 CY7C1339B-100AC CY7C1339B-100BGC CY7C1339B-100AI CY7C1339B-100BGI Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05141 Rev. *A Package Name Package Type A101 100-lead Thin Quad Flat Pack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead PBGA ( 2.4 mm) BG119 CY7C1339B 51-85115-*A Page ...
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... Document Title: CY7C1339B 128K x 32 Synchronous Pipelined Cache RAM Document Number: 38-05141 Issue REV. ECN NO. Date ** 109885 09/15/01 *A 113899 03/29/02 Document #: 38-05141 Rev. *A Orig. of Change SZV Change from Spec number: 38-00936 to 38-05141 SKX Changed the JTAG pins on the BGA package to DNU pins. ...