CY7C1356B-200AC Cypress Semiconductor Corp, CY7C1356B-200AC Datasheet
CY7C1356B-200AC
Specifications of CY7C1356B-200AC
Related parts for CY7C1356B-200AC
CY7C1356B-200AC Summary of contents
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... ZZ Cypress Semiconductor Corporation Document #: 38-05114 Rev. *C Functional Description The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B are ...
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... Logic Block Diagram-CY7C1356B (512K x 18) A0, A1, A MODE CLK C CEN WRITE ADDRESS ADV/ CE1 CE2 CE3 ZZ Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... DQa 18 63 DQa DQb DDQ 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1354B CY7C1356B DDQ DQPa 74 DQa 73 DQa DQa 69 DQa CY7C1356B (512K × 18 DQa 63 DQa DQa 59 DQa DDQ Page DDQ DDQ ...
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... Document #: 38-05114 Rev. *C 119-ball BGA Pinout CY7C1354B (256K × 36) – 14 × 22 BGA E(18 ADV/ DQP CLK CEN DQP MODE V DD E(72 TMS TDI TCK CY7C1356B (512K x 18)– BGA E(18 ADV/ CLK CEN DQP MODE E(36) TMS TDI TCK CY7C1354B CY7C1356B DDQ A CE ...
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... V b DDQ DDQ N DQP DDQ P NC E(72 MODE E(36) A Document #: 38-05114 Rev. *C 165-Ball fBGA Pinout CY7C1354B (256K × 36) – 13 × 15 fBGA CLK TDI TMS CY7C1356B (512K × 18) – 13 × 15 fBGA CLK TDI TMS CY7C1354B CY7C1356B ADV/LD CEN WE OE E(18 DDQ DDQ ...
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... Document #: 38-05114 Rev. *C Pin Description controls DQ and DQP a a and DQP , BW controls DQ and DQP select/deselect the device select/deselect the device select/deselect the device. 2 –DQ are placed in a three-state condition. The outputs are auto CY7C1354B CY7C1356B , BW controls DQ and DQP , During [a:d]. Page ...
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... On the next clock rise the data presented to DQ (DQ /DQP a,b,c,d CY7C1356B) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. The data written during the Write operation is controlled by BW ...
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... HIGH before presenting data (DQ /DQP for CY7C1354B and DQ a,b,c,d a,b,c,d CY7C1356B) inputs. Doing so will three-state the output drivers safety precaution, DQ DQP for CY7C1354B and a,b,c,d CY7C1356B) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses ...
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... OE is inactive or when the device is deselected, and DQs = data when OE is active. Document #: 38-05114 Rev. *C ADV/LD WE BWx OE CEN CLK CY7C1354B CY7C1356B DQ L-H Three-State L-H Three-State L-H Data Out (Q) L-H Data Out (Q) L-H Three-State L-H Three-State L-H Data In (D) L-H Data In (D) L-H Three-State L-H Three-State L Three-State = Three-state when [a:d] Page ...
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... Write Bytes Write Bytes d, c Write Bytes Write Bytes Write All Bytes Note: 8. Table only lists a partial listing of the byte write combinations. Any combination of BW Function (CY7C1356B) Read Write – No Bytes Written Write Byte a − (DQ and DQP a a) Write Byte b – (DQ ...
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... PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. CY7C1354B CY7C1356B Page ...
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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1354B CY7C1356B Page ...
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... RESET 1 TEST-LOGIC/ 0 IDLE Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05114 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1354B CY7C1356B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... I OL GND ≤ V ≤ DDQ GND ≤ V ≤ DDQ [12, 13] Over the Operating Range Description /2; undershoot: V (AC) > –0.5V for t < t /2. IL TCYC / ns CY7C1354B CY7C1356B 0 Selection 0 Circuitry 0 0 Min. Max. 2.0 1.7 2.0 2.0 0.7 0.2 1 0.3 DD –0.3 0.7 –30 30 –30 30 Min ...
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... TMSS t TMSH t TDIS t TDIH t TDOV CY7C1354B CY7C1356B 001 001 01010001000010110 Reserved for future use. 00000110100 00000110100 1 1 CY7C1354B CY7C1356B [12, 13] Min. Max ALL INPUT PULSES 3.0V 1.5V 1 TCYC t TDOX Description Reserved for version number. Allows unique identification of SRAM vendor. ...
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... Bit Size Description Boundary Scan Exit Order (×36) Bit # 165-Ball B10 31 A10 32 C11 33 E10 34 F10 35 G10 36 D10 37 D11 38 E11 39 F11 40 G11 41 H11 42 J10 43 K10 44 L10 45 M10 46 J11 CY7C1354B CY7C1356B (continued) 119-Ball ID 165-Ball ID M6 K11 L7 L11 K6 M11 P6 N11 T4 R11 A3 R10 C5 P10 Page ...
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... A9 B10 44 A10 A11 45 Not Bonded (Preset Not Bonded 47 (Preset Not Bonded 49 (Preset C11 51 D11 E11 52 CY7C1354B CY7C1356B (continued) 119-Ball ID 165-Ball ID G7 F11 H6 G11 T7 H11 K7 J10 L6 K10 N6 L10 P7 M10 Not Bonded Not Bonded (Preset to 0) (Preset to 0) Not Bonded Not Bonded ...
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... B2 65 Not Bonded (Preset Not Bonded (Preset Document #: 38-05114 Rev. *C (continued) 165-Ball Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset Not Bonded (Preset to 0) Not Bonded (Preset CY7C1354B CY7C1356B Page ...
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... /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1354B CY7C1356B Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% –40°C to +85°C Min. Max. 3.135 3.6 3.135 V DD 2.375 2.625 2 ...
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... V power is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ = 2.5V. DDQ CY7C1354B CY7C1356B BGA Max. fBGA Max. TQFP Max [16] ALL INPUT PULSES ...
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... CY7C1354B CY7C1356B -166 Min. Max. Unit 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 1.5 ns 0.5 ns 0.5 ns 0.5 ns 0 ...
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... D(A1) D(A2) Document #: 38-05114 Rev CLZ D(A1) D(A2) D(A2+1) BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) DON’T CARE UNDEFINED CY7C1354B CY7C1356B DOH t t OEV CHZ Q(A3) Q(A4) Q(A4+1) t OEHZ t DOH t OELZ BURST WRITE READ WRITE READ D(A5) Q(A6) D(A7) Q(A4+1) 9 ...
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... NOP,STALL AND DESELECT CYCLES 1 2 CLK CEN CE ADV/ ADDRESS Data In-Out (DQ) WRITE READ D(A1) Q(A2) Document #: 38-05114 Rev. *C [23,24,26 D(A1) Q(A2) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE CY7C1354B CY7C1356B D(A4) Q(A3) NOP READ DESELECT Q(A5) UNDEFINED Page CHZ Q(A5) CONTINUE DESELECT ...
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... Ordering Information Speed (MHz) Ordering Code 225 CY7C1354B-225AC CY7C1356B-225AC CY7C1354B-225AI CY7C1356B-225AI CY7C1354B-225BGC CY7C1356B-225BGC CY7C1354B-225BGI CY7C1356B-225BGI CY7C1354B-225BZC CY7C1356B-225BZC CY7C1354B-225BZI CY7C1356B-225BZI Document #: 38-05114 Rev ZZI I DDZZ High-Z DON’T CARE is LOW. When CE is HIGH,CE is HIGH Package Name A101 100-lead Thin Quad Flat Pack ( 1.4 mm) A101 100-lead Thin Quad Flat Pack ( ...
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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1354B-200AC CY7C1356B-200AC CY7C1354B-200AI CY7C1356B-200AI CY7C1354B-200BGC CY7C1356B-200BGC CY7C1354B-200BGI CY7C1356B-200BGI CY7C1354B-200BZC CY7C1356B-200BZC CY7C1354B-200BZI CY7C1356B-200BZI 166 CY7C1354B-166AC CY7C1356B-166AC CY7C1354B-166AI CY7C1356B-166AI CY7C1354B-166BGC CY7C1356B-166BGC CY7C1354B-166BGI CY7C1356B-166BGI CY7C1354B-166BZC CY7C1356B-166BZC CY7C1354B-166BZI CY7C1356B-166BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. ...
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... MIN. 1.00 REF. DETAIL Document #: 38-05114 Rev. *C DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1354B CY7C1356B 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05114 Rev. *C 119-Lead BGA ( 2.4mm) BG119 CY7C1354B CY7C1356B 51-85115-*B Page ...
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... NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05114 Rev. *C 165-Ball FBGA ( 1.2 mm) BB165A CY7C1354B CY7C1356B 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM NoBL™ Architecture Document Number: 38-05114 REV. ECN No. Issue Date ** 117904 08/28/02 *A 126207 08/27/03 *B 205060 See ECN *C 230388 See ECN Document #: 38-05114 Rev. *C Orig. of Change Description of Change RCS New Data Sheet ...