CY7C1356B-200AC Cypress Semiconductor Corp, CY7C1356B-200AC Datasheet - Page 15

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CY7C1356B-200AC

Manufacturer Part Number
CY7C1356B-200AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1356B-200AC

Lead Free Status / Rohs Status
Not Compliant
Document #: 38-05114 Rev. *C
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Identification Register Definitions
Hold Times
t
t
t
Output Times
t
t
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
TMSH
TDIH
CH
TDOV
TDOX
Parameter
TDO
Instruction Field
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after clock rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Z
Test Mode Select
TMS
Test Clock
TCK
Test Data-In
TDI
Test Data-Out
TDO
0
= 50Ω
(a)
1.25V for 2.5V V
1.5V for 3.3V V
GND
C
50Ω
L
01010001000100110
= 20 pF
DDQ
DDQ
00000110100
CY7C1354B
001
1
Over the Operating Range (continued)
Description
t
TMSS
t
TDIS
01010001000010110 Reserved for future use.
00000110100
t
CY7C1356B
TH
001
1
V
t
t
TDOV
SS
TL
t
t
TMSH
TDIH
1.5 ns
3.0V
Reserved for version number.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
t
TCYC
[12, 13]
t
TDOX
ALL INPUT PULSES
1.5V
Min.
10
10
10
0
Description
CY7C1356B
CY7C1354B
1.5 ns
Max.
20
Page 15 of 29
Unit
ns
ns
ns
ns
ns

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