CY7C1361B-100AJC Cypress Semiconductor Corp, CY7C1361B-100AJC Datasheet
CY7C1361B-100AJC
Specifications of CY7C1361B-100AJC
Related parts for CY7C1361B-100AJC
CY7C1361B-100AJC Summary of contents
Page 1
... Cypress Semiconductor Corporation Document #: 38-05302 Rev. *B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Functional Description The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with ) DD minimum glue logic. Maximum access delay from clock rise is 6 ...
Page 2
... Logic Block Diagram – CY7C1361B (256K x 36) ADDRESS A0, A1, A REGISTER MODE ADV CLK COUNTER AND LOGIC CLR ADSC ADSP DQ DQP , BYTE BYTE WRITE REGISTER WRITE REGISTER DQ DQP BYTE WRITE REGISTER DQ DQP , BYTE WRITE REGISTER DQP BYTE BWE WRITE REGISTER GW ENABLE CE1 ...
Page 3
... V DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1363B (512K x 18 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1361B CY7C1363B DDQ 76 V SSQ NC 75 DQP SSQ V 70 DDQ DDQ 60 V SSQ SSQ V 54 DDQ Page [+] Feedback ...
Page 4
... V DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ /DNU CY7C1363B (512K x 18 DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1361B CY7C1363B DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ DDQ V 60 SSQ SSQ V 54 DDQ Page [+] Feedback ...
Page 5
... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ Document #: 38-05302 Rev. *B 119-ball BGA (2 Chip Enables with JTAG) CY7C1361B (256K x 36 ADSP ADSC DQP ADV CLK BWE DQP MODE TMS TDI TCK TDO CY7C1363B (512K x 18 ADSP ...
Page 6
... DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M 288M DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05302 Rev. *B 165-ball fBGA (3 Chip Enable) CY7C1361B (256K x 36 BWE CLK 18M SS TDI A1 TDO A A0 TCK A ...
Page 7
... CY7C1361B–Pin Definitions TQFP TQFP (3-Chip (2-Chip Name Enable) Enable 37,36,32,33, 37,36,32,33 34,35,43,44, 34,35,44,45, 45,46,47,48, 46,47,48,49, 49,50,81,82, 50,81,82,92, 99,100 99,100 93,94,95,96 93,94,95,96 L5,G5,G3 CLK – [ ADV 84 84 ADSP Document #: 38-05302 Rev. *B BGA fBGA (2-Chip (3-Chip Enable) Enable) I/O P4,N4,A2, R6,P6,A2, Input- ...
Page 8
... CY7C1361B–Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable ADSC 87 87 BWE 52,53,56,57, 52,53,56,57 58,59,62,63, 58,59,62,63, 68,69,72,73, 68,69,72,73, 74,75,78,79, 74,75,78,79, 2,3,6,7,8,9, 2,3,6,7,8,9, 12,13,18,19, 12,13,18,19, 22,23,24,25, 22,23,24,25, 28,29 28,29 51,80,1,30 51,80,1,30 P6,D6,D2, DQP [A:D] MODE 15,41,65,91 15,41,65,91 J2,C4,J4 4,11,20,27, 4,11,20,27, ...
Page 9
... CY7C1361B–Pin Definitions (continued) TQFP TQFP (3-Chip (2-Chip Name Enable) Enable) V 17,40,67,90 17,40,67,90 H2,D3,E3 5,10,21,26, 5,10,21,26, SSQ 55,60,71,76 55,60,71,76 TDO – – TDI – – TMS – – TCK – – NC 16,38,39,42, 16,38,39,42, 66 43,66 V /DNU CY7C1363B: Pin Definitions TQFP TQFP (3-Chip ...
Page 10
... Asynchronous G4 A9 Input- Synchronous A4 B9 Input- Synchronous CY7C1361B CY7C1363B Description Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of ...
Page 11
... F7,J1,J7, D9,E3,E9, Supply M1,M7,U1 F3,F9,G3, ,U7 G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 CY7C1361B CY7C1363B Description Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A are [1:0] also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized ...
Page 12
... R1,R5,R7, N2,N5,N6, T1,T4,U6 N7,N10,N11, P1,P2,R2 – – Ground/DNU CY7C1361B CY7C1363B Description Ground for the core of the device. Ground for the I/O circuitry. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages ...
Page 13
... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1361B/CY7C1363B supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
Page 14
... CY7C1361B CY7C1363B Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H three-state L-H three-state L-H three-state L-H three-state L-H three-state three-state L L-H three-state L L L-H three-state L L-H three-state L L-H three-state L-H three-state L L-H three-state L L Writes may occur only on subsequent clocks after ...
Page 15
... Partial Truth Table for Read/Write Function (CY7C1361B) Read Read Write Byte (A, DQP ) A Write Byte (B, DQP ) B Write Bytes (B, A, DQP , DQP ) A B Write Byte (C, DQP ) C Write Bytes (C, A, DQP , DQP ) C A Write Bytes (C, B, DQP , DQP ) C B Write Bytes ( DQP , DQP , DQP ...
Page 16
... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1361B/CY7C1363B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
Page 17
... TAP controller’s capture setup plus t t hold time ( CS plus CH). The SRAM clock input might not be captured correctly if there portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1361B CY7C1363B Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
Page 18
... These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [9, 10] Over the operating Range Description /t = 1ns R F CY7C1361B CY7C1363B TDOV Min. Max. Unit MHz ...
Page 19
... V = 3.3V DDQ 8 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1361B CY7C1363B ......................................... V to 2.5V SS 1.25V 20pF O MIN MAX UNIT 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 ...
Page 20
... Describes the version number. 01010 01010 Reserved for Internal Use 000000 000000 Defines memory type and architecture 100110 010110 Defines width and density 00000110100 00000110100 Allows unique identification of SRAM vendor Indicates the presence register. Bit Size (x18 Description CY7C1361B CY7C1363B Description Page [+] Feedback ...
Page 21
... BGA Boundary Scan Order CY7C1361B (256K x 36) BALL Signal BIT# ID Name BIT# BALL ID 1 CLK BWE ADSC ADSP ADV DQP Internal DQP Internal Document #: 38-05302 Rev. *B CY7C1363B (512K x 18) Signal Signal Name BIT# BALL ID Name A0 1 CLK BWE ADSC ADSP ...
Page 22
... Boundary Scan Order CY7C1361B (256K x 36) BALL Signal BIT# ID Name BIT# BALL CLK BWE ADSC ADSP ADV 43 8 B10 A10 C11 DQP E10 F10 G10 D10 D11 E11 F11 DQ 53 Internal B 18 G11 H11 J10 K10 L10 M10 DQ 59 ...
Page 23
... All Speeds DD ≥ V ≤ 0.3V, – 0. /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1361B CY7C1363B Ambient Temperature DDQ 0°C to +70°C 3.3V – 5%/+10% 2.5V – Min. Max. Unit 3.135 3.6 3.135 ...
Page 24
... MHz 3.3V 2.5V DDQ R = 317Ω 3.3V V OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2. OUTPUT GND =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1361B CY7C1363B BGA fBGA Package Package Unit °C °C BGA fBGA Package Package Unit ...
Page 25
... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1361B CY7C1363B 117 MHz 100 MHz Max. Min. Max. Unit ...
Page 26
... ADVH ADVS ADV suspends burst t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1361B CY7C1363B Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state is HIGH LOW HIGH Page [+] Feedback ...
Page 27
... Full width write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05302 Rev. *B ADSC extends burst t t WES WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1361B CY7C1363B t ADS t ADH A3 t WES t WEH t ADVS t ADVH D(A3 Extended BURST WRITE Page [+] Feedback ...
Page 28
... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05302 Rev WES WEH OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1361B CY7C1363B A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
Page 29
... CY7C1361B-133AC CY7C1363B-133AC CY7C1361B-133AI CY7C1363B-133AI CY7C1361B-133AJC CY7C1363B-133AJC CY7C1361B-133AJI CY7C1363B-133AJI CY7C1361B-133BGC CY7C1363B-133BGC CY7C1361B-133BGI CY7C1363B-133BGI CY7C1361B-133BZC CY7C1363B-133BZC CY7C1361B-133BZI CY7C1363B-133BZI Document #: 38-05302 Rev. *B High-Z DON’T CARE Package Name Part and Package Type A101 100-lead Thin Quad Flat Pack ( 1.4 mm) 3 Chip Enables A101 100-lead Thin Quad Flat Pack ( ...
Page 30
... CY7C1361B-117BGC CY7C1363B-117BGC CY7C1361B-117BGI CY7C1363B-117BGI CY7C1361B-117BZC CY7C1363B-117BZC CY7C1361B-117BZI CY7C1363B-117BZI 100 CY7C1361B-100AC CY7C1363B-100AC CY7C1361B-100AI CY7C1363B-100AI CY7C1361B-100AJC CY7C1363B-100AJC CY7C1361B-100AJI CY7C1363B-100AJI CY7C1361B-100BGC CY7C1363B-100BGC CY7C1361B-100BGI CY7C1363B-100BGI CY7C1361B-100BZC CY7C1363B-100BGC CY7C1361B-100BZI CY7C1363B-100BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05302 Rev. *B ...
Page 31
... MAX. 0.60±0.15 0.20 MIN. 1.00 REF. A DETAIL Document #: 38-05302 Rev. *B DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 12°±1° TYP. (8X STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. CY7C1361B CY7C1363B 1.40±0.05 A SEE DETAIL 0.20 MAX. 1.60 MAX. 51-85050-*A Page [+] Feedback ...
Page 32
... Package Diagrams (continued) Document #: 38-05302 Rev. *B 119-Lead PBGA ( 2.4 mm) BG119 CY7C1361B CY7C1363B 51-85115-*B Page [+] Feedback ...
Page 33
... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1361B CY7C1363B 51-85122-*C ...
Page 34
... Document History Page Document Title: CY7C1361B/CY7C1363B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Document #: 38-05302 Rev. *B REV. ECN NO. Issue Date ** 116857 06/24/02 *A 206502 See ECN *B 225181 See ECN Document #: 38-05302 Rev. *B Orig. of Change Description of Change RCS New Data Sheet NJY Removed Preliminary status ...