CY7C1361B-100AJC Cypress Semiconductor Corp, CY7C1361B-100AJC Datasheet - Page 26

• Manufacturer Part Number: CY7C1361B-100AJC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AJC

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
Timing Diagrams
Read Cycle Timing
Note:
21. On this diagram, when CE is LOW: CE
GW, BWE,BW
Data Out (Q)
ADDRESS
CLK
ADSP
ADSC
ADV
OE
X
CE
High-Z
[21]
t ADS
t AS
t CES
A1
t ADH
t CLZ
t AH
t CEH
t
t OEV
CH
t CDV
t CYC
Single READ
t
t CL
WES
1
Q(A1)
is LOW, CE
t
WEH
t OEHZ
t ADS
A2
2
t ADH
is HIGH and CE
t OELZ
t
ADVS
Q(A2)
t DOH
t
ADVH
t CDV
3
is LOW. When CE is HIGH: CE
Q(A2 + 1)
DON’T CARE
Q(A2 + 2)
ADV suspends burst
UNDEFINED
BURST
READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
Q(A2)
Burst wraps around
to its initial state
CY7C1361B
CY7C1363B
3
Q(A2 + 1)
is HIGH.
Page 26 of 34
Deselect Cycle
Q(A2 + 2)
t CHZ
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