CY7C188-35VC Cypress Semiconductor Corp, CY7C188-35VC Datasheet

no-image

CY7C188-35VC

Manufacturer Part Number
CY7C188-35VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C188-35VC

Density
288Kb
Access Time (max)
35ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
15b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
160mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Word Size
9b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C188-35VC
Manufacturer:
CYPRESS
Quantity:
1 086
Part Number:
CY7C188-35VC
Manufacturer:
TI
Quantity:
221
Cypress Semiconductor Corporation
Document #: 38-05053 Rev. **
Features
Functional Description
The CY7C188 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 9 bits. Easy memory expansion is
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
Maximum Standby Current (mA)
• High speed
• Automatic power-down when deselected
• Low active power
• Low standby power
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
features
— 15 ns
— 660 mW
— 140 mW
CE
CE
WE
Logic Block Diagram
OE
1
2
A
A
A
A
A
A
A
0
1
2
3
4
5
6
INPUT BUFFER
DECODER
32K x 9
COLUMN
ARRAY
1
, CE
POWER
2
DOWN
, and OE
3901 North First Street
7C188–15
120
15
35
provided by an active-LOW chip enable (CE
chip enable (CE
three-state drivers. The device has an automatic power-down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking CE
enable (WE) inputs LOW and CE
nine I/O pins (I/O
ified on the address pins (A
Reading from the device is accomplished by taking CE
OE LOW while forcing WE and CE
ditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The nine input/output pins (I/O
pedance state when the device is deselected (CE
CE
write operation (CE
The CY7C188 is available in standard 300-mil-wide SOJs.
2
LOW), the outputs are disabled (OE HIGH), or during a
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
San Jose
C188–1
7C188–20
0
1
2
3
4
5
6
7
8
170
20
35
2
o
), an active-LOW output enable (OE), and
– I/O
1
LOW, CE
32K x 9 Static RAM
8
) is then written into the location spec-
Pin Configuration
0
CA 95134
– A
7C188–25
0
GND
2
I/O
I/O
I/O
I/O
– I/O
NC
NC
A
A
A
A
A
A
A
A
A
HIGH, and WE LOW).
14
0
1
2
3
5
4
3
2
1
0
8
7
6
165
25
35
2
).
2
Revised August 24, 2001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8
input HIGH. Data on the
DIP/SOJ
Top View
HIGH. Under these con-
) are placed in a high-im-
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
), an active-HIGH
CY7C188
408-943-2600
I/O
I/O
I/O
I/O
I/O
V
A
CE
WE
A
A
A
A
OE
A
CE
7C188–35
CC
14
13
9
10
11
12
8
7
6
5
4
2
1
1
C188–2
160
1
35
30
and write
HIGH or
1
and

Related parts for CY7C188-35VC

CY7C188-35VC Summary of contents

Page 1

... CMOS for optimum speed/power • TTL-compatible inputs and outputs • Easy memory expansion with CE features Functional Description The CY7C188 is a high-performance CMOS static RAM orga- nized as 32,768 words by 9 bits. Easy memory expansion is Logic Block Diagram INPUT BUFFER A 0 ...

Page 2

... MAX Max –0. 0.3V – 0. 0.3V Test Conditions MHz 5.0V CC CY7C188 [1] ................................. –0. Ambient Temperature + 7C188–20 7C188–25 7C188–35 Min. Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 0.3 + 0.3 + 0.3 –0.5 0.8 –0.5 0.8 – ...

Page 3

... LZWE Document #: 38-05053 Rev 481 255 INCLUDING JIGAND (b) C188–3 SCOPE 1.73V [2, 5] 7C188–15 7C188–20 Min. Max. Min [ ALLINPUTPULSES 3.0V 90% 10% GND 3 ns 7C188–25 7C188–35 Max. Min. Max. Min CY7C188 90% 10 C188–4 Max. Unit Page ...

Page 4

... Max. Min. Max. Min. , and t is less than t for any given device. LZOE HZWE LZWE and DATA VALID t HZOE t HZCE DATA VALID t PD 50% CY7C188 Max. Unit C188–5 HIGH IMPEDANCE ICC ISB C188–6 Page ...

Page 5

... During this period, the I/Os are in the output state and input signals should not be applied. Write Cycle No.2 (CE Controlled) ADDRESS DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) Document #: 38-05053 Rev PWE t SD DATA . IL and only the timing for [8,13,14,15 DATA [9,13,15 VALID IN is shown. 1 SCE VALID IN CY7C188 C188–7 C188–8 Page ...

Page 6

... V32 32-Lead (300-Mil) Molded SOJ V32 32-Lead (300-Mil) Molded SOJ V32 32-Lead (300-Mil) Molded SOJ V32 32-Lead (300-Mil) Molded SOJ DC Characteristics Parameter VALID IN t LZWE Power Standby ( Active ( Active ( Active ( Operating Range Commercial Commercial Subgroups SB1 SB2 CY7C188 C188–9 Page ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead (300-Mil) Molded SOJ V32 CY7C188 Page ...

Page 8

... Document Title: CY7C188 32K x 9 Static RAM Document Number: 38-05053 Issue REV. ECN NO. Date ** 107155 09/10/01 Document #: 38-05053 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00220 to 38-05053 CY7C188 Page ...

Related keywords