CY7C346B-25NC Cypress Semiconductor Corp, CY7C346B-25NC Datasheet
CY7C346B-25NC
Specifications of CY7C346B-25NC
Available stocks
Related parts for CY7C346B-25NC
CY7C346B-25NC Summary of contents
Page 1
... Each LAB is interconnected through the programmable inter- connect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C346B allow used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346B allows the replacement of over 50 TTL CY7C346B ...
Page 2
... I I GND 61 GND E I I I I/O I CY7C346B 7C346B-35 35 PGA Bottom View I/O I/O I/O INP INP INP INP V INP I/O CC I/O I/O I/O I/O INP GND INP V INP I/O CC I/O I/O GND INP INP I/O I/O I/O I/O ...
Page 3
... INPUT 20 INPUT 21 INPUT 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS PQFP Top View CY7C346B CY7C346B I I/O I I/O I/O 75 I/O 74 I/O 73 INPUT 72 INPUT 71 INPUT INPUT 67 INPUT 66 INPUT 65 INPUT 64 GND ...
Page 4
... Logic Array Blocks There are eight logic array blocks in the CY7C346B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array ...
Page 5
... The CY7C346B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow ...
Page 6
... Test Conditions 1.0 MHz 0V 1.0 MHz OUT R1 464Ω 250Ω INCLUDING JIG AND SCOPE (b) 1.75V parameter refers to low-level TTL output current. OL CY7C346B [1] .................... –25 mA to+25 mA [1] ........................................–2. 7.0V [2] Ambient Temperature ° ° +70 C ° ° – +85 C Min. Max. 4.75(4.5) 5 ...
Page 7
... This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the pF. Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS Description [4] [4] [4] [5] [6] Description [4] [7] [7] [6] 7C346B-25 Description Min. [4] [4] [ CY7C346B Over Operating Range 7C346B-25 7C346B-35 Min. Max. Min. Max 12.5 8 12.5 62.5 40 ...
Page 8
... REGISTERED OUTPUTS External Asynchronous DEDICATED INPUTS OR REGISTERED FEEDBACK ASYNCHRONOUS CLOCK INPUT Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS 7C346B-25 Description Min PD1 PD2 CO1 AS1 CY7C346B Over Operating Range (continued) 7C346B-35 Max. Min. Max AWH AWL Page Unit ...
Page 9
... CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY REGISTER OUTPUT TO ANOTHER LAB Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS EXP t AWL RSU LATCH FD t PIA CY7C346B LAC LAD t t COMB CLR PRE FD Page ...
Page 10
... DATA FROM LOGIC ARRAY Internal Synchronous CLOCK FROM LOGIC ARRAY t RD DATA FROM LOGIC ARRAY OUTPUT PIN Ordering Information Speed (ns) Ordering Code 25 CY7C346B-25HC/HI CY7C346B-25JC/JI CY7C346B-25NC/NI CY7C346B-25RC/RI 35 CY7C346B-35HC/HI CY7C346B-35JC/JI CY7C346B-35NC/NI CY7C346B-35RC/RI Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS t ICS ...
Page 11
... Package Diagrams Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS 84-leaded Windowed Leaded Chip Carrier H84 CY7C346B 51-80081-** Page ...
Page 12
... Package Diagrams (continued) Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS 84-lead Plastic Leaded Chip Carrier J83 CY7C346B 51-85006-*A Page ...
Page 13
... Package Diagrams (continued) Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS 100-Lead Plastic Quad Flatpack N100 CY7C346B 51-85052-*A Page ...
Page 14
... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 100-pin Windowed Ceramic Pin Grid Array R100 100-pin Windowed Ceramic Pin Grid Array R100 CY7C346B 51-80010-*C Page ...
Page 15
... Document History Page Document Title: CY7C346B 128-Macrocell Max Document Number: 38-03037 REV. ECN NO. Issue Date ** 106460 07/11/01 *A 113615 04/11/02 *B 122236 12/28/02 *C 213375 See ECN Document #: 38-03037 Rev. *C USE ULTRA37000™ FOR ALL NEW DESIGNS ® EPLD Orig. of Change Description of Change SZV ...