CY7C346B-25NC Cypress Semiconductor Corp, CY7C346B-25NC Datasheet - Page 7

• Manufacturer Part Number: CY7C346B-25NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C346B-25NC

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03037 Rev. *C
Commercial and Industrial External Synchronous Switching Characteristics
Commercial and Industrial External Asynchronous Switching Characteristics
Commercial and Industrial Internal Switching Characteristics
t
t
t
t
t
t
t
f
t
t
f
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
PD1
PD2
SU
CO1
H
WH
WL
MAX
CNT
ODH
CNT
ACO1
AS1
AH
AWH
AWL
ACNT
ACNT
IN
IO
EXP
LAD
LAC
OD
ZX
XZ
RSU
RH
LATCH
RD
4. C1 = 35 pF.
5. The f
6. This parameter is measured with a 16-bit counter programmed into each LAB.
7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t
8. C1 = 5 pF.
Parameter
Parameter
Parameter
MAX
values represent the highest frequency for pipeline data.
Dedicated Input to Combinatorial Output Delay
I/O Input to Combinatorial Output Delay
Global Clock Set-Up Time
Synchronous Clock Input to Output Delay
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency
Asynchronous Clock Input to Output Delay
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay
Output Buffer Disable Delay
Register Set-Up Time Relative to Clock Signal
at Register
Register Hold Time Relative to Clock Signal at
Register
Flow Through Latch Delay
Register Delay
Description
Description
Description
USE ULTRA37000™ FOR
ALL NEW DESIGNS
[4]
[8]
[4]
[5]
[7]
[7]
[4]
[4]
[6]
[6]
[4]
[4]
Min.
6
4
7C346B-25
Min.
62.5
15
50
Min.
0
8
8
2
7C346B-25
11
50
5
6
9
7C346B-25
Over Operating Range
Max.
12
12
10
10
10
5
6
5
3
1
Max.
Max.
25
40
14
20
25
20
ACH
and t
Min.
12
Min.
8
12.5
12.5
33.3
ACL
7C346B-35
25
40
Min.
33.3
0
2
7C346B-35
10
10
16
14
Over Operating Range
7C346B-35
Over Operating Range
parameter must be swapped.
CY7C346B
Max.
Max.
Max.
20
14
13
13
13
11
11
35
55
20
30
6
4
2
35
30
Page 7 of 15
MHz
MHz
Unit
Unit
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns