CYNSE70064A-83BGC Cypress Semiconductor Corp, CYNSE70064A-83BGC Datasheet - Page 98

• Manufacturer Part Number: CYNSE70064A-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-83BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70064A
11.0
Depth-Cascading
The Search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 272
bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. The latency of the
searches increases as the table size increases; the Search rate remains constant.
11.1
Depth-Cascading up to Eight Devices (One Block)
Figure 11-1 shows how up to eight devices can be cascaded to form 256K × 68, 128K × 136, or 64K × 272 tables. It also shows
the interconnection between the devices for depth-cascading. The LHO signal of a device is connected to LHI[6:0] signals of the
downstream devices. There is no specific order in which the LHO signal of a device is supposed to connect to the LHI signals of
the downstream devices. Each of the two LHO signals of a device, LHO[0] and LHO[1], can be connected to a maximum of 4 LHI
signals of other devices. Each Search engine asserts the LHO[1] and LHO[0] signals to inform downstream devices of its result
in case of a hit. The delay from the time search command is input into the device to the time LHO is asserted is constant, thats
is 4 clock cycles. Any device that receives an asserted LHI signal gives up its claim to drive read and write accesses to the SRAM.
The host ASIC must program the TLSZ to 01 for each of up to eight devices in a block. This adds the required latency to allow
time for the resolution about who drives the SRAM signals to take place. Only a single device drives the SRAM bus in any single
cycle.
Document #: 38-02041 Rev. *F
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