PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet

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PI7C8154B Asynchronous 2-Port PCI-to-PCI Bridge st 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Internet: http://www.pericom.com REVISION 1.12 Fax: 408-435-1100 ...

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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...

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REVISION HISTORY Date Revision Number 07/10/04 0.03 07/26/04 1.00 04/20/05 1.10 04/26/05 1.11 03/07/2006 1.12 06-0008 Description Initial release of preliminary specification Initial release of specification to the web Updated Power Dissipation in section 17.9 Updated T in sections 17.4 ...

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This page intentionally left blank. 06-0008 ASYNCHRONOUS 2-PORT Page 4 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...

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TABLE OF CONTENTS LIST OF TABLES...............................................................................................................................................10 LIST OF FIGURES.............................................................................................................................................10 INTRODUCTION ...............................................................................................................................................11 1 SIGNAL DEFINITIONS ...........................................................................................................................12 1.1 SIGNAL TYPES ................................................................................................................................12 1.2 SIGNALS ...........................................................................................................................................12 1.2.1 PRIMARY BUS INTERFACE SIGNALS ........................................................................................12 1.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ...................................................14 1.2.3 SECONDARY BUS ...

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TRANSACTION FLOW THROUGH ...............................................................................................37 2.11 TRANSACTION TERMINATION....................................................................................................37 2.11.1 MASTER TERMINATION INITIATED BY PI7C8154B............................................................38 2.11.2 MASTER ABORT RECEIVED BY PI7C8154B .........................................................................38 2.11.3 TARGET TERMINATION RECEIVED BY PI7C8154B............................................................39 2.11.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE ......................................................39 2.11.3.2 POSTED WRITE TARGET TERMINATION RESPONSE.........................................................40 ...

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SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER .......................................66 7.2.4 BUS PARKING ..............................................................................................................................66 8 GENERAL PURPOSE I/O INTERFACE ...............................................................................................67 8.1 GPIO CONTROL REGISTERS.........................................................................................................67 8.2 SECONDARY CLOCK CONTROL..................................................................................................68 8.3 LIVE INSERTION .............................................................................................................................69 9 EEPROM INTERFACE............................................................................................................................69 9.1 AUTO MODE EEPROM ACCESS ...................................................................................................70 ...

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CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................83 14.1.27 INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................83 14.1.28 INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................83 14.1.29 BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................83 14.1.30 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET ...

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TAP PINS ................................................................................................................................101 16.1.2 INSTRUCTION REGISTER ....................................................................................................101 16.2 BOUNDARY SCAN INSTRUCTION SET ....................................................................................102 16.3 TAP TEST DATA REGISTERS......................................................................................................102 16.4 BYPASS REGISTER .......................................................................................................................103 16.5 BOUNDARY SCAN REGISTER ....................................................................................................103 16.6 TAP CONTROLLER .......................................................................................................................103 17 ELECTRICAL AND TIMING SPECIFICATIONS.............................................................................108 17.1 MAXIMUM RATINGS ...

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LIST OF TABLES T 2-1 PCI TRANSACTIONS.......................................................................................................................23 ABLE T 2-2 WRITE TRANSACTION FORWARDING.......................................................................................25 ABLE T 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................................27 ABLE T 2-4 READ PREFETCH ADDRESS BOUNDARIES ...............................................................................29 ABLE T 2-5 READ TRANSACTION PREFETCHING.........................................................................................29 ABLE T 2-6 DEVICE ...

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... INTRODUCTION Product Description The PI7C8154B is Pericom Semiconductor’s PCI-to-PCI Bridge, designed to be fully compliant with the 64-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8154B supports synchronous and asynchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz. For the PI7C8154B-80, the Secondary Bus supports up to 80MHz operation ...

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SIGNAL DEFINITIONS 1.1 SIGNAL TYPES Signal Type STS OD 1.2 SIGNALS Note: Signal names that end with “#” are active LOW. 1.2.1 PRIMARY BUS INTERFACE SIGNALS Name Pin # P_AD[31:0] U2, U4, U1, V2, V1, ...

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Name Pin # P_IRDY# AC5 P_TRDY# AB5 P_DEVSEL# AA6 P_STOP# AC6 P_LOCK# AB6 P_IDSEL Y1 P_PERR# AC7 P_SERR# Y7 P_REQ# U3 P_GNT# R2 P_RESET# R3 06-0008 ASYNCHRONOUS 2-PORT Type Description STS Primary IRDY (Active LOW). Driven by the initiator of ...

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Name Pin # P_M66EN AB10 1.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # P_AD[63:32] AA16, AB16, AA17, AB17, Y17, AB18, AC18, AA18, AC19, AA19, AB20, Y19, AA20, AB21, AC21, AA21, Y20, AA23, Y21, W20, Y23, W21, W23, ...

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Name Pin # P_REQ64# AC14 P_ACK64# AB14 1.2.3 SECONDARY BUS INTERFACE SIGNALS Name Pin # S_AD[31:0] C3, A3, B3, C4, A4, B4, C5, B5, A6, A7, D7, B7, A8, B8, C8, A9, C13, B13, A13, D13, C14, B14, C15, B15, ...

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Name Pin # S_TRDY# A10 S_DEVSEL# B10 S_STOP# C10 S_LOCK# A11 S_PERR# C11 S_SERR# B11 S_REQ#[8:0] E1, E3, D2, D1, E4, D3, C2, C1, D4 S_GNT#[8:0] H1, G3, G2, G4, G1, F2, F1, F3, E2 S_RESET# H2 S_M66EN A14 S_CFN# ...

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SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION Name Pin # S_AD[63:32] C20, A21, D20, C21, C23, C22, D21, E20, D22, E21, E23, F21, F23, F22, G20, G22, G21, H23, H22, H21, J23, J20, J22, K23, K22, K21, L23, L21, L22, ...

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Name Pin # S_CLKIN J4 S_CLKOUT[9:0] P1, P2, P3, N1, N3, M2, M1, M3, L3, L2 ASYNC_SEL# AB1 ASYNC_CLKIN AB2 1.2.6 MISCELLANEOUS SIGNALS Name Pin # MSK_IN R21 P_VIO R20 S_VIO N22 BPCCE R4 06-0008 ASYNCHRONOUS 2-PORT Type Description I ...

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CONFIG66 R22 PMEENA# D11 EEDATA A22 EECLK A23 EE_EN# AC22 NO CONNECT B6, AA22 1.2.7 GENERAL PURPOSE I/O INTERFACE SIGNALS Name Pin # GPIO[3:0] K2, K3, L4, L1 1.2.8 JTAG BOUNDARY SCAN SIGNALS Name Pin # TCK N20 TMS P21 ...

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Name Pin # VSS A1, A5, A12, A16, B2, B21, B22, C7, D8, D12, D16, D23, F4, F20, G23, H3, J2, K4, K20, L20, N2, P4, P20, T2, U21, V4, V20, Y8, Y9, Y12, Y16, AA2, AB22, AC1, AC4, AC13, ...

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BALL PIN NAME LOCATION E1 S_REQ#[8] E3 S_REQ#[ E21 S_AD[54] E23 S_AD[53] F1 S_GNT#[2] F3 S_GNT#[ F21 S_AD[52] F23 S_AD[51] G1 S_GNT#[4] G3 S_GNT#[ G21 S_AD[47] G23 VSS H1 S_GNT#[8] H3 VSS - - ...

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BALL PIN NAME LOCATION - - U21 VSS U23 P_AD[36] V1 P_AD[27] V3 P_AD[26 V21 P_AD[39] V23 P_AD[38] W1 P_AD[24] W3 VDD - - W21 P_AD[42] W23 P_AD[41] Y1 P_IDSEL Y3 P_AD[22] Y5 P_AD[16] Y7 P_SERR# Y9 VSS ...

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BALL PIN NAME LOCATION AC19 P_AD[55] AC21 P_AD[49] AC23 VSS 2 SIGNAL DEFINITIONS This Chapter offers information about PCI transactions, transaction forwarding across PI7C8154B, and transaction termination. The PI7C8154B has two 128-byte buffers for read data buffering of upstream and ...

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PCI buses, either upstream or downstream, Type 1 configuration write must be used. PI7C8154B neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary ...

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Depending on the command type, PI7C8154B can support multiple data phase PCI transactions. For detailed descriptions of how PI7C8154B imposes disconnect boundaries, see Section 2.6.4 for write address boundaries and Section 2.7.3 read address boundaries. 2.6 WRITE TRANSACTIONS Write transactions ...

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PI7C8154B ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C8154B starts another transaction to ...

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PI7C8154B claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8154B also asserts STOP# in conjunction with TRDY# to signal a target disconnect. ...

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Delayed write transactions are accepted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 4 for information ...

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If extra read transactions could have side effects, for example, when accessing a FIFO, use non- prefetchable read transactions to those locations. Accordingly important to retain the value of the byte enable bits during the data phase, ...

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PI7C8154B accepts a delayed read request, by sampling the read address, read bus command, and ...

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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read ...

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Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and ...

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The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3: configuration read or ...

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TYPE 1 TO TYPE 1 FORWARDING Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C8154B detects a Type 1 configuration transaction intended for a ...

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The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back ...

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TRANSACTIONS – DATA PHASE PI7C8154B asserts REQ64# to indicate it is initiating a 64-bit transfer during memory write transactions. During the data phase, PI7C8154B asserts the following: The low 32 bits of data on AD[31:0] The low 4 ...

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TRANSACTIONS – SUPPORT DURING RESET PI7C8154B checks P_REQ64# while P_RESET# is asserted to determine whether the 64-bit extensions are connected. If P_REQ64# ...

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FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be deasserted on the next clock cycle following detection of the master abort condition. The target can terminate transactions with one of the following types of ...

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This sets the received-master-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, PI7C8154B is able to reflect the master abort condition back to the initiator. When PI7C8154B ...

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Target Termination Normal Target Retry Target Disconnect Target Abort After the PI7C8154B makes 2 target bus, PI7C8154B asserts P_SERR# if the SERR# enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is ...

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PI7C8154B repeats a delayed read transaction until one of the following conditions is met: PI7C8154B completes at least one data transfer. PI7C8154B receives a master abort. PI7C8154B receives a target abort. 24 PI7C8154B makes 2 Table 2-9 RESPONSE TO DELAYED ...

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The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at head of the read ...

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TARGET ABORT PI7C8154B returns a target abort to an initiator when one of the following conditions is met: PI7C8154B is returning a target abort from the intended target. When PI7C8154B returns a target abort to the initiator, it sets ...

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If the master-enable bit is not set, PI7C8154B ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions if ...

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ISA MODE PI7C8154B supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of PI7C8154B inside the I/O address range in order to support mapping of I/O ...

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MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be pre-fetched but that can be conditionally pre-fetched based on command type should be mapped into this space. ...

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PI7C8154B does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that ...

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If the prefetchable memory space on the secondary bus resides entirely in the first 4GB of memory, both upper 32 bit register must be set to 0. PI7C8154B then ignores all dual address cycles initiated on the primary interface and ...

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FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. PI7C8154B requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in ...

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Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite ...

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The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for PI7C8154B and must also be true for other bus agents. ...

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Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to ...

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If the parity error response bit is set in the command register, PI7C8154B does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8154B ...

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READ TRANSACTIONS When PI7C8154B detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when PI7C8154B detects a read data parity error ...

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If the parity-error-response bit corresponding to the initiator bus is set, PI7C8154B asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles ...

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Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8154B has write status to return, the following events occur: PI7C8154B first asserts S_TRDY# and then asserts S_PERR# two cycles later; if the ...

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During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target’s assertion of S_PERR#, the following events occur: Bridge sets the data parity detected bit in the status register of secondary interface, ...

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Primary Detected Transaction Type Parity Error Bit 0 Posted Write 0 Posted Write 0 Posted Write 1 Delayed Write 0 Delayed Write 0 Delayed Write 0 Delayed Write Note: x=don’t care Table 5-2 shows setting the detected parity error bit ...

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Table 5-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: The PI7C8154B must be a master on the secondary bus. The parity error response bit must ...

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PI7C8154B detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Table 5-6 ASSERTION OF S_PERR# S_PERR# Transaction Type 1 (de-asserted) Read ...

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For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. Whenever the bridge asserts P_SERR#, PI7C8154B must also set the signaled system error bit in the status register. In compliance ...

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The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved. 6.2.1 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION Locked ...

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The first transaction to establish LOCK# must be Memory Read. If the first transaction is not Memory read, the following transactions behave accordingly: Type 0 Configuration Read/Write induces master abort. Type 1 Configuration Read/Write induces master abort. I/O Read induces ...

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When PI7C8154B receives a target abort or a master abort in response to a locked posted write transaction, PI7C8154B cannot pass back that status to the initiator. PI7C8154B asserts SERR# on the initiator bus when a target abort or a ...

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The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 4 requests / grants. Each set of masters can be assigned to a high priority group and a low priority group. The low priority ...

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S_FRAME# or S_IRDY# is asserted, the arbiter can be de-asserted one grant and asserted another grant during the same PCI clock cycle. 7.2.2 PREEMPTION Preemption can be programmed to be either on or off, with the default to on (offset ...

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GENERAL PURPOSE I/O INTERFACE The PI7C8154B implements a 4-pin general purpose I/O interface. During normal operation, device specific configuration registers control the GPIO interface. The GPIO interface can be used for the following functions: During secondary interface reset, the ...

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SECONDARY CLOCK CONTROL The PI7C8154B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock ...

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Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8154B’s S_CLKIN input. If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8154B’s S_CLKIN input can be rearranged from the assignment shown here. However, it ...

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EEPROM is used to initialize a select number of registers. This is accomplished after P_RESET# is deasserted, at which time the data from the EEPROM will be loaded. The EEPROM interface is organized into a 16-bit base, and the bridge ...

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EEPROM BYTE ADDRESS 04 – 05h 06 – 07h 08h 09h 0A – 0Bh 0Ch 0Dh 0E – 0Fh 10 – 11h 12h 13h 14h 15 – 16h 17 – 18h 19 – 1Ch 1D – 20h 21 – 22h ...

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SECONDARY CLOCK OUTPUTS The bridge has 10 secondary clock outputs, S_CLKOUT[9:0], that can be used as clock inputs for up to nine external secondary bus devices. In synchronous mode (ASYNC_SEL# = 1), the S_CLKOUT[9:0] outputs are derived from P_CLK. ...

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Current Status HOT D3 D3 COLD D3 D0 COLD PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges. 13 RESET This chapter describes the primary interface, secondary ...

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When S_RESET# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately tri-stated. Signals S_AD[31:0], S_CBE[3:0], S_PAR are driven low for the duration of S_RESET# assertion. S_REQ64# is asserted LOW to indicate 64-bit extension support ...

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CONFIGURATION REGISTERS PCI configuration defines a 64 DWORD space to define various attributes of PI7C8154B as shown below. Table 14-1 CONFIGURATION SPACE MAP 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory ...

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SIGNAL TYPES Signal Type R/O R/W R/WC R/WR R/WS 14.1.2 VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID 14.1.3 DEVICE ID REGISTER – OFFSET 00h Bit Function 31:16 Device ID 14.1.4 COMMAND REGISTER – OFFSET 04h ...

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Bit Function VGA Palette 5 Snoop Enable Parity Error 6 Response Wait Cycle 7 Control 8 P_SERR# enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.5 STATUS REGISTER – OFFEST 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz ...

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Bit Function 27 Signaled Target Abort 28 Received Target Abort 29 Received Master Abort 30 Signaled System Error 31 Detected Parity Error 14.1.6 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 14.1.7 CLASS CODE REGISTER – OFFSET 08h ...

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HEADER TYPE REGISTER – OFFSET 0Ch Bit Function 23:16 Header Type 14.1.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 7:0 Primary Bus Number 14.1.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 15:8 Secondary Bus Number ...

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Bit Function 7:4 I/O Base Address [15:12] 14.1.16 I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 9:8 32-bit Indicator 11:10 Reserved 15:12 I/O Limit Address [15:12] 14.1.17 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function 20:16 Reserved 21 66MHz Capable ...

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Bit Function Detected Parity 31 Error 14.1.18 MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 Reserved 15:4 Memory Base Address [15:4] 14.1.19 MEMORY LIMIT REGISTER – OFFSET 20h Bit Function 19:16 Reserved 31:20 Memory Limit Address [31:20] 14.1.20 PREFETCHABLE ...

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PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h Bit Function 19:16 64-bit addressing 31:20 Prefetchable Memory Limit Address [31:20] 14.1.22 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable Memory Base Address, Upper 32-bits ...

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CAPABILITY POINTER REGISTER – OFFSET 34h Bit Function 7:0 Enhanced Capabilities Port Pointer 14.1.27 INTERRUPT LINE REGISTER – OFFSET 3Ch Bit Function 7:0 Interrupt Line 14.1.28 INTERRUPT PIN REGISTER – OFFSET 3Ch Bit Function 15:8 Interrupt Pin 14.1.29 BRIDGE ...

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Bit Function 19 VGA enable 20 Reserved 21 Master Abort Mode 22 Secondary Interface Reset 23 Fast Back-to- Back Enable 24 Primary Master Timeout 25 Secondary Master Timeout 26 Master Timeout Status 27 Discard Timer P_SERR# enable 06-0008 Type Description ...

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Bit Function 31-28 Reserved 14.1.30 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit Function 0 Reserved 1 Memory Write Disconnect Control 3:2 Reserved 4 Secondary Bus Prefetch Disable 5 Live Insertion Mode 7:6 Reserved 8 Chip Reset 15:9 Reserved ...

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Bit Function 26 Broken Master Timeout Enable 27 Automatic Preemption Control 31:28 Reserved 14.1.32 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h Bit Function Memory Read 0 Flow Through Disable 1 Park Downstream ( Memory 2 Read Dynamic Prefetching ...

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Bit Function Memory Read 4 Underflow Control 15:5 Reserved 14.1.33 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( Memory Base and Limit Enable 31:17 Reserved 14.1.34 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET ...

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EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h Bit Function 15:0 Reserved EEPROM 16 Autoload Control Fast EEPROM 17 Autoload Control EEPROM 18 Autoload Status 31:19 Reserved 14.1.37 EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h Bit Function ...

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UPSTREAM ( MEMORY BASE ADDRESS REGISTER – OFFSET 58h Bit Function 64-bit 3:0 Addressing Upstream 15:4 Memory Base 14.1.40 UPSTREAM ( MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h Bit Function 64-bit 19:16 Addressing Upstream 31:20 ...

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Bit Function Posted Write 1 with Parity Error Posted Write 2 with Non- Delivery Data Target Abort 3 During Posted Write Master Abort 4 During Posted Write Delayed Write 5 with Non- Delivery Delayed Read 6 Without Data From Target ...

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GPIO DATA AND CONTROL REGISTER – OFFSET 64h Bit Function GPIO output 11:8 write-1-to-clear GPIO output 15:12 write-1-to-set GPIO output 19:16 enable write-1- to-clear GPIO output 23:20 enable write-1- to-set 27:24 Reserved GPIO Input Data 31:28 Register 14.1.45 SECONDARY ...

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Bit Function S_CLKOUT[2] 5:4 disable S_CLKOUT[3] 7:6 disable S_CLKOUT[4] 8 disable S_CLKOUT[5] 9 disable S_CLKOUT[6] 10 disable S_CLKOUT[7] 11 disable S_CLKOUT[8] 12 disable S_CLKOUT[9] 13 disable 15:14 Reserved 06-0008 Type Description S_CLKOUT[2] (slot 2) Enable 00: enable S_CLKOUT[2] 01: enable ...

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P_SERR# STATUS REGISTER – OFFSET 68h Bit Function Address Parity 16 Error Posted Write 17 Data Parity Error Posted Write 18 Non-delivery Target Abort 19 during Posted Write Master Abort 20 during Posted Write Delayed Write 21 Non-delivery Delayed ...

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Bit Function Secondary Memory Write 4 Command Alias Enable Primary Memory Read 5 Line/Multiple Alias Enable Secondary Memory Read 6 Line/Multiple Alias Enable Primary Memory Write and 7 Invalidate Command Alias Disable Secondary Memory Write 8 and Invalidate Command Alias ...

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Bit Function Ordering Rules 13 Control 2 15:14 Reserved 14.1.48 SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h Bit Function Secondary 15:0 Master Timeout 14.1.49 PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h Bit Function Primary Master 31:16 Timeout 14.1.50 ...

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CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function 31:24 Chassis Number 14.1.54 CAPABILITY ID REGISTER – OFFSET DCh Bit Function Enhanced 7:0 Capabilities ID 14.1.55 NEXT ITEM POINTER REGISTER – OFFSET DCh Bit Function Next Item 15:8 Pointer 14.1.56 ...

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Bit Function 12:9 Data Select 14:13 Data Scale 15 PME status 14.1.58 PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h Bit Function 21:16 Reserved 22 B2_B3 Bus Power/Clock 23 Control Enable 14.1.59 DATA REGISTER – OFFSET E0h Bit Function 31:24 Data ...

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Bit Function PI (Programming 21:20 Interface) EXT (ENUM# 22 Status – Extraction) INS (ENUM# 23 Status – Insertion) 31:24 Reserved 14.1.63 CAPABILITY ID REGISTER – OFFSET E8h Bit Function 7:0 Capability ID 14.1.64 NEXT POINTER REGISTER – OFFSET E8h Bit ...

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BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME# signal bridge, there are a number of possibilities. Those possibilities are summarized in the table below: 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES Initiator Master on ...

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REPORTING PARITY ERRORS For all address phases parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then tri-stating two cycles after the bad address. P_SERR# can ...

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TAP pins, instruction register, test data registers and TAP controller. Figure 16-1 illustrates how these pieces fit together to form the JTAG unit. Figure 16-1 TEST ACCESS PORT DIAGRAM 16.1.1 TAP PINS The PI7C8154B’s ...

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Upon activation of the TRST# reset pin, the latched instruction asynchronously changes to the id code instruction. When the TAP controller moves into the test state other than by reset activation, the opcode changes as TDI shifts, and becomes active ...

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BYPASS REGISTER The required bypass register, a one-bit shift register, provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the ...

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Table 16-2 JTAG BOUNDARY REGISTER ORDER Boundary-Scan Register Number ...

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Boundary-Scan Register Number ...

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Boundary-Scan Register Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 ...

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Boundary-Scan Register Number 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 ...

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ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AV Voltage at Input Pins Junction Temperature, ...

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AC SPECIFICATIONS Figure 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal ...

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PCI SIGNALING TIMING Symbol Parameter T SKEW among S_CLKOUT[9:0] SKEW T DELAY between PCLK and S_CLKOUT[9:0] DELAY T P_CLK, S_CLKOUT[9:0] cycle time CYCLE T P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 17.6 RESET TIMING ...

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... PBGA PACKAGE DIAGRAM Figure 18-1 304-BALL PBGA PACKAGE OUTLINE Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php 18.2 ORDERING INFORMATION Part Number PI7C8154BNA PI7C8154BNAE PI7C8154BNA-80 PI7C8154BNAE-80 PI7C8154BNAI PI7C8154BNAIE 06-0008 Typical 1.38 417 Speed Pin – Package 66MHz 304 – PBGA 66MHz 304 – ...