PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 10

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
LIST OF TABLES
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
LIST OF FIGURES
F
F
F
F
IGURE
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
04
......................................................................................................................................................................58
2-1 PCI TRANSACTIONS.......................................................................................................................23
2-2 WRITE TRANSACTION FORWARDING.......................................................................................25
2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................................27
2-4 READ PREFETCH ADDRESS BOUNDARIES ...............................................................................29
2-5 READ TRANSACTION PREFETCHING.........................................................................................29
2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING ....................................................................33
2-7 DELAYED WRITE TARGET TERMINATION RESPONSE ..........................................................39
2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION .......................................................40
2-9 RESPONSE TO DELAYED READ TARGET TERMINATION .....................................................41
4-1 SUMMARY OF TRANSACTION ORDERING ................................................................................51
5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT (
5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT.........................58
5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (
5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT ...........................59
5-5 ASSERTION OF P_PERR# ...............................................................................................................59
5-6 ASSERTION OF S_PERR# ...............................................................................................................60
5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS...........................................................60
8-1 GPIO OPERATION............................................................................................................................68
8-2 GPIO SERIAL DATA FORMAT.......................................................................................................68
11-1 VALID ASYNCHRONOUS CLOCK FREQUENCIES ..................................................................72
12-1 POWER MANAGEMENT TRANSITIONS ....................................................................................72
14-1 CONFIGURATION SPACE MAP...................................................................................................75
16-1 TAP PINS .......................................................................................................................................102
16-2 JTAG BOUNDARY REGISTER ORDER.....................................................................................104
7-1 SECONDARY ARBITER EXAMPLE .............................................................................................65
16-1 TEST ACCESS PORT DIAGRAM...............................................................................................101
17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS..........................................................109
18-1 304-BALL PBGA PACKAGE OUTLINE ....................................................................................111
H
) ..............................................................................................................................................................57
Page 10 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
BIT
BIT
24
31
OF OFFSET
OF OFFSET
PI7C8154B
04
H
)