74LVC1G07GW NXP Semiconductors, 74LVC1G07GW Datasheet - Page 2

• Manufacturer Part Number: 74LVC1G07GW
• Manufacturer: NXP Semiconductors

Specifications of 74LVC1G07GW

• Logic Family: LVC
• Logical Function: Buffer/Driver
• Number Of Elements: 1
• Number Of Channels: 1
• Number Of Inputs: 1
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: TSSOP
• Output Type: Open Drain
• Polarity: Non-Inverting
• Propagation Delay Time: 8.4ns
• Low Level Output Current: 32mA
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.65V
• Quiescent Current: 200uA
• Technology: CMOS
• Pin Count: 5
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
[1]
5. Functional diagram
74LVC1G07
Product data sheet
Type number
74LVC1G07GW
74LVC1G07GV
74LVC1G07GM
74LVC1G07GF
74LVC1G07GN
74LVC1G07GS
Type number
74LVC1G07GW
74LVC1G07GV
74LVC1G07GM
74LVC1G07GF
74LVC1G07GN
74LVC1G07GS
Fig 1.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
2
Logic symbol
Ordering information
Marking
A
Package
Temperature range Name
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
mna623
Y
4
TSSOP5
SC-74A
XSON6
XSON6
XSON6
XSON6
All information provided in this document is subject to legal disclaimers.
Fig 2.
Rev. 9 — 24 August 2010
A
IEC logic symbol
2
plastic extremely thin small outline package;
plastic extremely thin small outline package;
extremely thin small outline package; no leads;
extremely thin small outline package; no leads;
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic surface-mounted package; 5 leads
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
no leads; 6 terminals; body 1 × 1 × 0.5 mm
6 terminals; body 0.9 × 1.0 × 0.35 mm
6 terminals; body 1.0 × 1.0 × 0.35 mm
Marking code
VS
V07
VS
VS
VS
VS
mna624
4
Y
[1]
Fig 3.
Buffer with open-drain output
A
Logic diagram
74LVC1G07
© NXP B.V. 2010. All rights reserved.
GND
Y
Version
SOT353-1
SOT753
SOT886
SOT891
SOT1115
SOT1202
mna591
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