HD74HC164FPEL Renesas Electronics America, HD74HC164FPEL Datasheet - Page 3

• Manufacturer Part Number: HD74HC164FPEL
• Manufacturer: Renesas Electronics America
• Type: Not Requiredr

Specifications of HD74HC164FPEL

• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logic Family: HC
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOP
• Propagation Delay Time: 220ns
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / Rohs Status: Not Compliant

HD74HC164
8-bit Parallel-out Shift Register
Description
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock pulse. A high level on the input enables the other input which
will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or
low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and
out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and
accomplished by a low level at the clear input.
Features
Note:
Function Table
Q
Q
H :
L :
X :
REJ03D0580-0400 Rev.4.00 Mar 25, 2009
Page 1 of 7
HD74HC164P
HD74HC164FPEL
HD74HC164RPEL
Ao
An
High Speed Operation: t
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
Low Input Current: 1 A max
Low Quiescent Supply Current: I
Ordering Information
Clear
to Q
to Q
H
H
H
H
Part Name
L
Please consult the sales office for the above package availability.
High level
Low level
Irrelevant
Ho
Gn
= Outputs remain unchanged.
= Data shifted from the previous stage on a positive edge at the clock input.
Clock
X
SOP-14 pin (JEDEC)
Inputs
SOP-14 pin (JEITA)
pd
Package Type
DILP-14 pin
(Clock to Q) = 14.5 ns typ (C
CC
= 2 to 6 V
A
X
X
X
H
L
CC
(static) = 4 A max
B
X
X
X
H
L
(Previous Code)
PRDP0014AB-B
PRSP0014DE-A
PRSP0014DF-B
Package Code
(FP-14DAV)
(FP-14DNV)
(DP-14AV)
L
= 50 pF)
Q
Q
H
L
L
L
Ao
A
Abbreviation
Package
Q
Q
Q
Q
Q
RP
L
FP
Bo
An
An
An
P
B
Outputs
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
·········
·········
·········
·········
·········
·········
Taping Abbreviation
REJ03D0580-0400
(Quantity)
Mar 25, 2009
Rev.4.00
Q
Q
Q
Q
Q
L
Ho
Gn
Gn
Gn
H