AM29LV001BB-90EC Spansion Inc., AM29LV001BB-90EC Datasheet - Page 16

• Manufacturer Part Number: AM29LV001BB-90EC
• Manufacturer: Spansion Inc.

Specifications of AM29LV001BB-90EC

• Cell Type: NOR
• Density: 1Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 17b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
min g o peration. Th e B yte Pro gram comma nd
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
“0” back to a “1”. Attempting to do so may halt the oper-
ation and set DQ5 to “1,” or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read shows that the data is still
“0”. Only erase operations can convert a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time.
for the command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares for both cycles. The device then returns
to reading array data.
Figure 3
ation. See the table
page 28
timing diagrams.
14
for parameters, and
illustrates the algorithm for the program oper-
Table 5 on page 17
“Write Operation Status” on page 18
“Erase/Program Operations” on
Figure 15, on page 29
shows the requirements
D A T A S H E E T
Am29LV001B
for
Note: See
sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
page 17
the chip erase command sequence.
Any commands wr itten to the chip dur ing the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
Increment Address
shows the address and data requirements for
Table 5 on page 17
Figure 3. Program Operation
in progress
Embedded
algorithm
Program
No
for program command
Command Sequence
21557F4 May 5, 2006
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
Table 5 on
No