HEF4059BT NXP Semiconductors, HEF4059BT Datasheet - Page 4

• Manufacturer Part Number: HEF4059BT
• Manufacturer: NXP Semiconductors
• Type: Decader

Specifications of HEF4059BT

• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 5
• Logic Family: 4000
• Logical Function: Counter/Divider
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: SO
• Propagation Delay Time: 200ns
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 15V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Figure 3 illustrates the operation of the counter in mode
If the ‘master preset’ mode is started two clock cycles or
less before an output pulse, the output pulse will appear at
the time due. If the ‘master preset’ mode is not used the
counter is preset in accordance with the ‘jam inputs when
the output pulse appears. A HIGH level at the latch enable
input (EL) will cause the counter output to go HIGH once
an output pulse occurs, and remain in the HIGH state until
EL input returns to LOW. If the EL input is LOW, the output
pulse will remain HIGH for only one cycle of the clock input
signal.
January 1995
Programmable divide-by-n counter
CP INPUT
K
(K
internal state
O OUTPUT
c
of counter
a
INPUT
, K
b
= LOW)
Fig.3 Total count of 3.
8 starting from the preset state 3.
4
When K
operates in the ‘preset inhibit’ mode, with which the
dividend of the counter is fixed to 10 000, independent of
the state of the jam inputs.
When in the same state of mode select inputs EL = H, the
counter operates in the normal
without the latch operation at the output.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
a
= L, K
b
= H, K
c
= L and EL = L, the counter
10 mode, however,
Product specification
HEF4059B
LSI