RC82544GC Intel, RC82544GC Datasheet
RC82544GC
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Gigabit Ethernet Controller The 82544EI/82544GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. 82544EI/82544GC Specification Update October ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548- 4725 or by visiting Intel’s web site at http://www.Intel.com. ...
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CONTENTS CONTENTS .....................................................................................................................................................1 PREFACE .......................................................................................................................................................4 NOMENCLATURE ..........................................................................................................................................4 COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE ............................................................5 GENERAL INFORMATION .............................................................................................................................5 82544EI/82544GC Component Marking Information .................................................................................5 SUMMARY TABLE OF CHANGES .................................................................................................................7 Codes Used in Summary Tables...............................................................................................................7 SPECIFICATION CHANGES......................................................................................................................... 10 1. TCP Segmentation (Large Send Offload)....................................................................................... ...
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SPECIFICATION UPDATE 28. Unexpected RCMP ACK packets in ASF mode.............................................................................. 20 29. Exceeding PCI Power Management Specification Limit of 375mA current during reset and power state transitions..................................................... 20 30. Memory Access must be enabled in order to Read Device ...
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REVISION HISTORY 82544EI/82544GC Gigabit Ethernet Controller Specification Update Date of Revision April 1, 2004 August 3, 2004 January 10, 2005 October 10, 2005 82544EI/82544GC SPECIFICATION UPDATE Description Initial public release. Added errata # 25 – 27. Added Errata # 28, ...
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... SPECIFICATION UPDATE PREFACE This document is an update to published specifications. Specification documents for this product include: • 82544EI Gigabit Ethernet Controller Hardware Design Guide Application Note (AP-422), Intel Corporation. • 82544GC Gigabit Ethernet Controller Hardware Design Guide Application Note (AP-427), Intel Corporation. • ...
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... Q483 FW82544EI - FW82544EI - NH82544EI Q476 RC82544GC Q477 RC82544GC Q480 RC82544GC Q482 RC82544GC Q484 RC82544GC - RC82544GC Notes Engineering Samples Engineering Samples Engineering Samples Internal Engineering Only Engineering Samples Production Units Lead-Free Production Units Engineering Samples Engineering Samples Engineering Samples Internal Engineering Only ...
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... SPECIFICATION UPDATE Note: Devices that are lead-free are marked with a circled “e1” and have a product code: NH82544EI. 6 ® FW82544EI Intel©'ZZ YYWW Tnnnnnnnn Country RC82544GC Intel©'ZZ YYWW Tnnnnnnnn Country ...
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... The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed 82544EI/82544GC steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following ...
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SPECIFICATION UPDATE No Plans Spec Change TCP Segmentation (Large Send Offload No Plans ...
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No Plans NoFix NoFix NoFix NoFix ...
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SPECIFICATION UPDATE SPECIFICATION CHANGES 1. TCP Segmentation (Large Send Offload) Problem: Due to multiple issues with regards to TCP segmentation (Large Send Offload) using the 82544EI/GC Ethernet Network Controllers, it was de-featured and thereby not supported. Affected Docs: 82544EI ...
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... PME# assertion and wakeup. Implication: Spurious wakeups are possible in response to undersize wakeup packets. Such packets are not expected to occur in normal LAN operation. Workaround: None. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controller. 82544EI/82544GC SPECIFICATION UPDATE 11 ...
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... Software drivers that rely on a mixture of delayed and non-delayed transmit interrupts may not work satisfactorily. Workaround: Use the delayed interrupt feature for all transmit descriptor interrupts, or for none of them. Intel drivers typically use IDE=1 for all descriptors, but program diminishing timer values into TIDV when buffer resources are low. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controller ...
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... Workaround: The chipset has a register setting to allow for greater than 8 clock cycles GNT# to #FRAME timing. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/GC Gigabit Ethernet Controller. 82544EI/82544GC SPECIFICATION UPDATE 13 ...
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... TEST1 instead of No Connect. The factory test pin that is already named “TEST” will be renamed to TEST0 for consistency. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/GC Gigabit Ethernet Controller. 14 ...
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... Other operating systems treat 0x0000 and 0xFFFF as equivalent in one’s complement math. UDP checksums are correct. Workaround: Intel modified the DOS Ethernet driver to check for a received checksum of 0xFFFF on a TCP/IP packet and change it back to 0x0000 before passing the packet to the operating system. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controller ...
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... Additionally, use the default value for PTHRESH and avoid non-default values of WTHRESH in RXDCTL (0x02828) unless specifically recommended by Intel. Intel changed the Linux driver to no longer use RDTR. Other Intel drivers did not previously use the feature. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controllers ...
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... Program the APM Enable Bit in the EEPROM (Bit 2 of Initialization Control Word 2 at offset 0x0F Contact your Intel representative for details on how to change settings in the EEPROM. The driver can still activate APM mode by setting APME in the WUC Register prior to going into a D3 state. ...
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... Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controllers. 18 NC_N2 (82544EI) / ...
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... For PCI systems, advertisement of the MSI capability can be turned off by setting the MSI Disable bit in the EEPROM (Init Control Word 2, bit 7). For PCI-X systems where MSI support is enumerated as part of the PCI-X specification, Intel is working with OS vendors to ensure that any future implementations of their operating systems can detect these products and avoid using the MSI mechanism ...
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... If and only if a host bridge also has a similar dependency, the possibility of a deadlock exists. A situation may arise where the bridge is waiting for the controller to respond to a DWord read while the controller is waiting for the bridge to complete a block read. Workaround: None. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controllers. 20 ...
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... This would create a situation where the only way to trigger the erratum was for the link partner to have a faster clock which would violate the 802.3 standard. Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controller. 82544EI/82544GC SPECIFICATION UPDATE ...
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... In terms of registers, the PHY’s transmitter can be powered down by writing: Write Register 0x1D = 0x0019 Write Register 0x1E = 0xFFFF It can be re-enabled by writing: Write Register 0x1D = 0x0019 Write Register 0x1E = 0xFFF0 Write Register 0x1E = 0xFF00 Status: Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet Controller. 22 ...
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SPECIFICATION CLARIFICATIONS 1. Receiver Enabling and Disabling Problem: The 82544EI/82544GC controller does not support “throttled” reception by repeatedly disabling/enabling the receiver by programming the Enable (EN) Bit in the Receive Control Register (RCTL). The reason is that the disabling/enabling operation ...
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SPECIFICATION UPDATE 2. Octets Transmitted Counters Adjusted if VLAN Enabled Problem: When the controller is configured to enable transmission of VLAN packets (CTRL.VME = 1), the device automatically adds 4 to the bytes counted in the Good Octets Transmitted ...
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Former Signal Ball Ball Name Number Number A4 D4 TX_DATA0 D5 D5 TX_DATA1 C5 C4 TX_DATA2 A5 E4 TX_DATA3 D6 C5 TX_DATA4 B6 E5 TX_DATA5 A6 B5 TX_DATA6 D7 E6 TX_DATA7 D8 D7 TX_DATA8 A7 C7 TX_DATA9 C7 ...
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SPECIFICATION UPDATE 82544EI 82544GC Ball Ball Number Number B13 C11 A12 B10 Affected Docs: 82544EI Gigabit Ethernet Controller Hardware Design Guide Application Note (AP-422), Rev. 0.77, document number A44740-003 and 82544GC Gigabit Ethernet Controller Hardware Design Guide Application Note ...
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Register Function Setting 29.4:0 Test mode 11010 = gig receiver control 29.4:0 Test mode 11111 = G clks, Fiber, TBT, SD Gig Receiver control (Test mode = 11010) Register Function Setting 30_26.15 Override 1 = Enable 30_26.14:0 Override 30_26.14:12 Unused ...
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SPECIFICATION UPDATE used to force transmit descriptor status bytes to be written back to memory as the packet data reaches the transmit queue. Affected text includes 4.3.2 Transmit Descriptor Writeback and references in numerous other sections, including the interrupt ...