RC82544GC Intel, RC82544GC Datasheet - Page 20

• Manufacturer Part Number: RC82544GC
• Manufacturer: Intel

Specifications of RC82544GC

• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 364
• Lead Free Status / Rohs Status: Not Compliant

Problem:
Implication:
Workaround:
Problem:
Implication:
Workaround:
82544EI/82544GC SPECIFICATION UPDATE
23. Intermittent Power-on State Due to Decoded High-Impedance Test Modes
Status:
24. 32-Bit Split-Completion Dependency on subsequent REQ64#
Status:
18
If on power-up, in configurations where the AUX_PWR indication is asserted to a logic “1”, and the following
decoded NO_CONNECT pins power on with logic input values shown in the table below, then the high-
impedance tri-state mode will be decoded, and the internal pull-up resistors will be disabled resulting in a
possible behavior that is intermittent or erratic.
encodings listed above, the pull-ups will be enabled, and the pins will be pulled up to their nominal operational
values. The 82544EI/82544GC may be reset to a mostly operational state by subsequent PCI device resets.
However, PCI I/O impendence settings may remain improperly configured until a subsequent
LAN_PWR_GOOD reset.
The affected NO_CONNECT pin is L4 on the 82544EI controller and pin J5 on the 82544GC controller.
Attaching an external pull-up resistor to this pin ensures that the two potential high-impedance modes are not
improperly decoded. Future revisions of product documentation will indicate this ball as TEST2 instead of
NO_CONNECT.
If the last few bytes of a transmit DMA fetch are lost due to this erratum, the internal DMA client will stall; waiting
for its remaining data, in which a transmit hang may be observed. If the subsequent data-fetch operation
represents a descriptor-fetch operation, the erroneous residual data path content may corrupt the fetched
descriptor. Resulting in potential data addressing errors, including unexpected Dual-Address Cycles (DAC),
system memory protection errors, and/or system hangs.
To workaround this erratum, each data buffer should be checked to determine whether the final byte of the
buffer resides at a host memory offset of 0x0-0x3 or 0x8-0xB within a Quadword memory alignment. If so,
terminate the descriptor buffer reference at an odd-word address alignment such as 0x7 or 0xF, and utilize a
second data descriptor to reference the final 1-8 bytes of data.
The 82544EI/82544GC contains internal logic which decodes various test mode(s) for component and/or
system-level production test. The decoding of the various test modes is performed based on four component
input pins listed in the table below. Three of the decoded pins are designated as NO_CONNECT in
documentation because the pins provide internal pull-up resistors. However, two of the test mode operations
place I/O pins in tri-state / high-impedance mode, which disable the internal pull-up resistors.
During this high-impedance tri-state mode, if/when the three NO_CONNECT pins drift to values other than the
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controllers.
The 82544EI/82544GC contains an elasticity FIFO to convert requested data from the PCI/PCI-X bus width into
128-bit internal data widths. When operating as a PCI-X bus segment, an error may occur, if the last few bytes
of a requested transmit-DMA operation are returned in a 32-bit split-completion. If the last 32-bit transfer cycle
of the requested DMA transfer is followed immediately on the bus by a single-cycle bus turnaround and 64-bit
external transaction request, the REQ64# signal from the subsequent transaction improperly affects the internal
data path pipeline from the just-completed 32-bit split-completion.
The error may occur when the ending address of a transmit-data descriptor buffer terminates within even-dword
alignment (the final data byte of the burst is located at a memory address ending in 0x0...0x3 or 0x8...0xB).
When the error occurs, an internal data path pointer fails to be updated properly. The resulting pointer error
may result in transmit data being lost, and/or incorrect residual data being delivered to subsequent data fetch
operations.
Due to PCI-X bus protocols, transfers of 8 bytes or less which are performed as 32-bit split-completions are not
susceptible to this problem, due to the existence of an extra clock cycle between the final data phase and the
bus turn-around cycle.
Intel does not plan to resolve this erratum in a future stepping of the 82544EI/82544GC Gigabit Ethernet
Controllers.
AUX_PWR
1
1
NC_L4 (82544EI) /
NC_J5 (82544GC)
0
0
NC_N2 (82544EI) /
NC_L4 (82544GC)
1
0
NC_M2 (82544EI) /
NC_K3 (82544GC)
0
1
Tri-state/ High-Z w/
pull-ups disabled
Decoded Test
Mode