PPC440GX-3RF800C Applied Micro Circuits Corporation, PPC440GX-3RF800C Datasheet - Page 12

• Manufacturer Part Number: PPC440GX-3RF800C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3RF800C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 800MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.6V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: CBGA
• Lead Free Status / Rohs Status: Compliant

440GX – Power PC 440GX Embedded Processor
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DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs,
and other discrete devices. Up to four 512MB logical banks are supported in limited configurations. Global memory
timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
External Peripheral Bus Controller (EBC)
Features include:
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
• Registered and non-registered industry standard DIMMs
• 64-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 2.6GB/s peak bandwidth at 166MHz (200MHz for 800MHz Rev F parts)
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• DDR200/266/333 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)
• Up to eight ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
• Up to 83.33MHz operation (333MB/s)
• Burst and non-burst devices
• 8-, 16-, 32-bit byte-addressable data bus
• 32-bit address, 4GB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
• Programmable address mapping
• External DMA Slave Support
- Single beat I/O reads and writes
- Single beat and burst memory reads and writes
- Single beat configuration reads and writes (type 0 and type 1)
- Single beat special cycles
- 256 Wait States for non-burst
- 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Revision 1.19 – December 19, 2008
Data Sheet
AMCC