S29GL128N11FAI020 Spansion Inc., S29GL128N11FAI020 Datasheet - Page 16

• Manufacturer Part Number: S29GL128N11FAI020
• Manufacturer: Spansion Inc.

Specifications of S29GL128N11FAI020

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 24/23Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: Fortified BGA
• Program/erase Volt (typ): 3/11.5 to 12.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 16M/8M
• Supply Current: 90mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

7.4
16
7.3.1
7.4.1
7.4.2
7.4.3
Writing Commands/Command Sequences
Page Mode Read
Write Buffer
Accelerated Program Operation
Autoselect Functions
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
timing specifications and to
table for the active current specification on reading array data.
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)–A3.
Address bits A2–A0 in word mode (A2–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to t
locations specified by the microprocessor falls within that page) is equivalent to t
asserted and reasserted for a subsequent access, the access time is t
are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to V
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The
“Word Program Command Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 7.4 on page
Refer to the DC Characteristics table for the active current specification for the write mode. The AC
Characteristics section contains timing specification tables and timing diagrams for write operations.
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. See
Write Buffer on page 16
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at
the factory.
If the system asserts V
mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
operation. Note that the WP#/ACC pin must not be at V
programming, or device damage may result. WP# has an internal pull-up; when unconnected, WP# is at V
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. Refer to the
Autoselect Command Sequence on page
Reading Array Data on page 48
35, and
HH
for more information.
on this pin, the device automatically enters the aforementioned Unlock Bypass
Table 7.5 on page 38
Figure 15.1 on page 72
for more information. Refer to the AC Read-Only Operations table for
S29GL-N
49, for more information.
D a t a
ACC
indicate the address space that each sector occupies.
or t
HH
for the timing diagram. Refer to the DC Characteristics
CE
from the WP#/ACC pin returns the device to normal
S h e e t
HH
and subsequent page read accesses (as long as the
for operations other than accelerated
IL
, and OE# to V
Autoselect Mode on page 38
ACC
or t
CE
IH
S29GL-N_00_B8 May 30, 2008
Table 7.2 on page
PACC
. Fast page mode accesses
.
. When CE# is de-
and
18,
IH
.