S29GL128N11FAI020 Spansion Inc., S29GL128N11FAI020 Datasheet - Page 51

no-image

S29GL128N11FAI020

Manufacturer Part Number
S29GL128N11FAI020
Description
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29GL128N11FAI020

Cell Type
NOR
Density
128Mb
Access Time (max)
110ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
24/23Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
Fortified BGA
Program/erase Volt (typ)
3/11.5 to 12.5V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
16M/8M
Supply Current
90mA
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant
D a t a
S h e e t
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 =
toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for
the next operation.
Write buffer programming is allowed in any sequence. Note that the Secured Silicon sector, autoselect, and
CFI functions are unavailable when a program operation is in progress. This flash device is capable of
handling multiple write buffer programming operations on the same write buffer address range without
intervening erases. Any bit in a write buffer address range cannot be programmed from 0 back to a 1.
Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate
the operation was successful. However, a succeeding read shows that the data is still 0. Only erase
operations can convert a 0 to a 1.
9.5.3
Accelerated Program
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V
HH
on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write
the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/
ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V
for operations other than
HH
accelerated programming, or device damage may result. WP# has an internal pull-up; when unconnected,
WP# is at V
.
IH
Figure 9.2 on page 53
illustrates the algorithm for the program operation. Refer to
Erase and Program
Operations on page 75
for parameters, and
Figure 15.4 on page 76
for timing diagrams.
May 30, 2008 S29GL-N_00_B8
S29GL-N
51

Related parts for S29GL128N11FAI020