21154BC Intel, 21154BC Datasheet - Page 17

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

5.
Problem:
Implication:
Workaround:
Status:
6.
Problem:
Implication:
Workaround:
21154 PCI-to-PCI Bridge Specification Update
Note: This errata only applies to applications that use the 21154 for secondary clocks.
64-Bit Data Bus Width not Maintained when Transitioning from PCI Bus
Power Management States D3 to D0
When transitioning from PCI Bus Power Management states D3 hot to D0 hot, the 21154 performs
an internal reset of the primary bus circuits and clears the REQ64 status of the primary bus. The
secondary bus continues to operate at 64-bit data bus width but the primary bus width reverts back
to a 32-bit data bus width. The 21154 drives the AD<63:32> with whatever data is next in its queue
and may drive incorrect parity for AD<63:32> as well.
The 21154 can cause bus contention on AD<63:32> resulting in data corruption and device
damage. This erratum may also cause some systems to hang or report parity errors.
This problem can be avoided by treating the 21154 as a PCI Bus Power Management legacy device
by not using the PCI Bus Power Management capabilities.
Fixed
Secondary Clocks Outputs s_clk_o<9:0> May Not Start-up Properly Under
Some Conditions
This problem has been found on the 21154AC and 21154BC. Under repeated and frequent power
cycling, the secondary clock circuits may not power up in the proper state, resulting in the device
not coming out of reset after power up.
In a system with a 21154AC or 21154BC that has one of its s_clk_o<9:0> outputs fed back to
provide the s_clk, it is possible that the s_clk_o<9:0> output clocks will be driven and remain low,
keeping s_rst_l asserted, during system power up.
This happens occasionally when a latch whose output disables the serial shift registers on the
Secondary clock control powers up in a high state and the shift register bit corresponding to the
s_clk_o<9:0> output that is fed back also powers up in the high state.
Two workarounds are provided for this errata:
1.
•
•
The first is the recommended workaround which ensure proper operation of the secondary
clock outputs s_clk_0<0:9>.
The second workaround ensures the secondary clock outputs operate properly but could result
in contention between the s_ckl_0 output and the buffer.
Figure 1
gated via the B0 input of the multiplexer to the S_Clock_in pin of the 21150.
At time 0, the S input of the multiplexer is low, allowing pulses from the on-board pulse
source, connected to the B0 input, to be provided to the 21150 S_Clk input pin. When the time
determined by the R/C network is satisfied, the S input pin will be in a logic High state. The
multiplexer will then shut off the input pulse from S0 and will direct the S_Clock_out pulses
via the B1 multiplexer input, into S_Clock_in
The values used for the R/C network should be selected to allow a minimum of 2 pulses to be
delivered to the 21150 after Vdd has reached 3.0V at a frequency not to exceed the appropriate
PCI component. i.e. 30 ns for a 33Mhz bridge. These values should be chosen based on the rise
time of the power supply and the frequency of the on board pulse source. The values given for
R1, R3, and C1 are for example purposes only.
illustrates the first recommendation - a circuit where an on-board pulse source is
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Errata