21154BC Intel, 21154BC Datasheet - Page 19

• Manufacturer Part Number: 21154BC
• Manufacturer: Intel

Specifications of 21154BC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Figure 2.
Status:
7.
Problem:
21154 PCI-to-PCI Bridge Specification Update
Note: This errata does not apply when operating at 33 MHz or if the external shift register is not used and
Recommended Circuit for a Tristable Buffer
Fixed
GPIO 66 MHz Timing May Cause Secondary Clocks to be Disabled
In the Secondary Clock Control function, the msk_in pin may be used with an external shift
register to selectively disable secondary clock output pins. At 66 MHz the timing of the interface
between the gpio pins and the external shift register may cause some secondary clock outputs to be
incorrectly disabled.
The setup time of the recommended 74F166 shift register is not compatible with the timing of the
gpio<2>, and gpio<0> outputs of the 21154 PCI-to-PCI bridge. Pin gpio<2> driving the shift
register load/shift enable (PE#), does not provide the necessary setup time for the gpio<0>. Signal
gpio<0> is used as a clock to initiate the parallel load of the 74F166 shift register data inputs. The
timing is referred to as Tgsval.
msk_in is grounded enabling all secondary clocks.
The following should be considered in calculating the R1,C1 time constant:
— Make the time constant of the circuit as short as possible, while still ensuring that a
— Phase delay between s_clk_o and the external clock should be minimized.
— Matching the external clock and s_clk_o frequencies to reduce contention.
— Laboratory experiments using p_clk as the external clock and a R1C1 time constant
minimum of two pulses are generated during the Vcc ramp.
between 40 and 60 percent of the Vcc ramp have been successful using this configuration.
However the use of p_clk as the external clock violates the PCI bus specification for
loading of the primary clock.
V
CC
R1
C1
External
Clock
R2
R3
S_CLK
S_CLK_O
Intel Confidential19
A8363-01
Errata