SCANSTA112VS National Semiconductor, SCANSTA112VS Datasheet - Page 2
![](/photos/40/57/405716/100pin_tqfp_sml.jpg)
SCANSTA112VS
Manufacturer Part Number
SCANSTA112VS
Description
Manufacturer
National Semiconductor
Datasheet
1.SCANSTA112VS.pdf
(15 pages)
Specifications of SCANSTA112VS
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
TQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SCANSTA112VS
Manufacturer:
NS
Quantity:
8
Company:
Part Number:
SCANSTA112VS
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
SCANSTA112VS
Manufacturer:
NS/国半
Quantity:
20 000
Company:
Part Number:
SCANSTA112VS/NOPB
Manufacturer:
National Semiconductor
Quantity:
135
Company:
Part Number:
SCANSTA112VS/NOPB
Manufacturer:
NSC
Quantity:
311
Company:
Part Number:
SCANSTA112VS/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
SCANSTA112VS/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Company:
Part Number:
SCANSTA112VSX
Manufacturer:
Texas Instruments
Quantity:
10 000
Company:
Part Number:
SCANSTA112VSX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
www.national.com
Introduction
The SCANSTA112 is the third device in a series that enable
multi-drop address and multiplexing of IEEE-1149.1 scan
chains. The SCANSTA112 is a superset of its predecessors
- the SCANPSC110 and the SCANSTA111. The STA112 has
all features and functionality of these two previous devices.
The STA112 is essentially a support device for the IEEE
1149.1 standard. It is primarily used to partition scan chains
into managable sizes, or to isolate specific devices onto a
seperate chain (Figure 1). The benefits of multiple scan
chains are improved fault isolation, faster test times, faster
programiing times, and smaller vector sets.
In addition to scan chain partitioning, the device is also
addressable for use in a multidrop backplane environment
(Figure 2). In this configuration, multiple IEEE-1149.1 acces-
sible cards with an STA112 on board can utilize the same
backplane test bus for system-level IEEE-1149.1 access.
This approach facilitates a system-wide commitment to
structural test and programming throughout the entire sys-
tem life sycle.
FIGURE 2. Example of SCANSTA112 in a multidrop addressable backplane.
2
Architecture
Figure 3 shows the basic architecture of the ’STA112. The
device’s major functional blocks are illustrated here.
The TAP Controller, a 16-state state machine, is the central
control for the device. The instruction register and various
test data registers can be scanned to exercise the various
functions of the ’STA112 (these registers behave as defined
in IEEE Std. 1149.1).
The ’STA112 selection controller provides the functionality
that allows the 1149.1 protocol to be used in a multi-drop
environment. It primarily compares the address input to the
slot identification and enables the ’STA112 for subsequent
scan operations.
The Local Scan Port Network (LSPN) contains multiplexing
logic used to select different port configurations. The LSPN
control block contains the Local Scan Port Controllers
(LSPC) for each Local Scan Port (LSP
control block receives input from the ’STA112 instruction
register, mode registers, and the TAP controller. Each local
port contains all four boundary scan signals needed to inter-
face with the local TAPs plus the optional Test Reset signal
(TRST).
The TDI/TDO Crossover Master/Slave logic is used to define
the bidirectional B0 and B1 ports in a Master/Slave
configuration.
20051251
0
, LSP
1
... LSP
n
). This