CY7C1514V18-250BZXC Cypress Semiconductor Corp, CY7C1514V18-250BZXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1514V18-250BZXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1514V18-250BZXC

• Density: 72Mb
• Access Time (max): 0.45ns
• Sync/async: Synchronous
• Architecture: QDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 1.8V
• Address Bus: 21b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 950mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / Rohs Status: Compliant

Pin Definitions
Document #: 38-05489 Rev. *F
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
V
V
V
V
V
V
Pin Name
SS
SS
REF
DD
SS
DDQ
/144M
/288M
Power Supply Power Supply Inputs to the Core of the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Echo Clock
Echo Clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
N/A
IO
(continued)
CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in
CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, connect this pin directly to V
impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the operation with the DLL turned off differs from those listed in this data sheet.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Address expansion for 144M. Can be tied to any voltage level.
Address expansion for 288M. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the Device.
[x:0]
Switching Characteristics
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Switching Characteristics
Pin Description
CY7C1510V18, CY7C1525V18
CY7C1512V18, CY7C1514V18
on page 23.
on page 23.
DDQ
, which enables the minimum
Page 7 of 29
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