S5920Q Applied Micro Circuits Corporation, S5920Q Datasheet - Page 142
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S5920Q
Manufacturer Part Number
S5920Q
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet
1.S5920Q.pdf
(165 pages)
Specifications of S5920Q
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
PQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S5920Q
Manufacturer:
AMCC
Quantity:
5 510
- Current page: 142 of 165
- Download datasheet (3Mb)
S5920 – PCI Product: Pass-Thru Operation
Figure 76. Active Mode 32-Bit PCI Write w/PTWAIT#
Clock by Clock description of Figure 16
Clock 1: The S5920 drives PTATN# and PTBURST#
active (low), indicating the start of a PCI to Add-On
data transfer with more than one data cycle. PTBE[3:0]
and PTNUM[1:0] are driven to their appropriate values
for this transfer. PTWR is driven high indicating a
Pass-Thru write.
Clock 2: Since this region does not have PTADR#
enabled as an output and PTWAIT# is high at the ris-
ing edge of clock 2, the first data transfer is indicated
by driving DXFR# low and the data on the data bus
DQ[31:0] .
Clock 3: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the first data word at the rising edge of this clock.
Valid data is determined by decoding the PTBE[3:0]#
lines. The Add-On device drives PTWAIT# active (low)
requesting a wait state on the next cycle.
Clock 4: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the second data word at this clock edge.
The S5920 tri-states its output bus since PTWAIT#
was inactive (high) at the rising edge of clock 4. Addi-
tionally, the S5920 deasserts DXFR# indicating that no
data transfer will occur on the next clock edge (this is
because this cycle is a wait state since PTWAIT# was
active (low) at the rising edge of clock 4. The Add-On
device deasserts PTWAIT# indicating no wait state on
the next clock.
AMCC Confidential and Proprietary
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTBE[3:0]#
DXFR#
DQ[31:0]
PTADR#
PTWAIT#
ADCLK
0
1
2
Data1 Data2
DATA1
3
DATA2
4
Data3
5
01b
DATA3
6
Clock 5: No data transfer takes place at the rising
edge of clock 5 since the previous cycle was an Add-
On initiated wait state (because PTWAIT# was active
(low) at the rising edge of clock 4). The S5920 asserts
DXFR# and drives the third data onto the DQ bus
since PTWAIT# was inactive (high) at the rising edge
of clock 5. The Add-On device drives PTWAIT# active
(low) requesting a wait state on the next cycle.
Clock 6: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the third data word at the rising edge of this
clock. The S5920 drives DXFR# inactive and tri-states
the DQ bus since PTWAIT# was active (low) at the ris-
ing edge of clock 6. The Add-On keeps PTWAIT#
asserted indicating it wants to add a wait state on the
next cycle.
Clock 7: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 6).
Clock 8: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On-initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 7). DXFR# is
driven active (low) and the fourth data is driven onto
the DQ bus since PTWAIT# was inactive (high) at the
rising edge of clock 8. PTBURST# is driven inactive
(high) indicating that after this data word is transferred,
there is only one data word left to transfer.
7
Data4
8
DATA4
9
Data5
DATA5
Revision 1.02 – April 12, 2007
10
Fh
11
Data Book
12
DS1596
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142
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