UDA1380HN NXP Semiconductors, UDA1380HN Datasheet - Page 30

• Manufacturer Part Number: UDA1380HN
• Manufacturer: NXP Semiconductors

Specifications of UDA1380HN

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
11.1
Table 17 Register address 00H
Table 18 Description of register bits
2004 Apr 22
Symbol
Default
Symbol
Default
Stereo audio coder-decoder
for MD, CD and MP3
BIT
BIT
15 to 13
7 and 6
Evaluation modes and clock settings
BIT
12
11
10
9
8
5
EV2
15
0
7
−
0
EV[2:0]
−
EN_ADC
EN_DEC
EN_DAC
EN_INT
−
ADC_CLK
SYMBOL
EV1
14
0
6
−
0
Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for
manufacturer’s evaluation and must always be kept at their default values for
normal operation of UDA1380; default value 000.
default value 0
ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK
input) to the analog part of the ADC. See Fig.5 for more detailed information.
When this bit is logic 0: clock to ADC disabled and when this bit is logic 1:
clock to ADC running. Default value 0.
Decimator clock enable. A 1-bit value to enable the 128f
decimator, the 128f
L3-bus or I
this bit is logic 0: clock to the decimator disabled. When this bit is logic 1:
clock to the decimator running. Default value 1.
FSDAC clock enable. A 1-bit value to enable the 256f
part of the FSDAC. See Fig.5 for more detailed information. When this bit is
logic 0: clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC
running. Default value 0.
Interpolator clock enable. A 1-bit value to enable the 128f
interpolator, the 128f
registers of the L3-bus or I
information. When this bit is logic 0: clock to the interpolator disabled. When
this bit is logic 1: clock to the interpolator running. Default value 1.
default value 00
ADC clock select. A 1-bit value to select the 128f
analog part for the decimator and the ADC. This can either be the clock
derived from the SYSCLK input or from the WSPLL. When this bit is logic 0:
SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0.
ADC_CLK
EV0
13
0
5
0
2
C-bus registers. See Fig.5 for more detailed information. When
DAC_CLK
12
30
−
0
4
0
s
part of the I
s
part of the I
2
C-bus interface. See Fig.5 for more detailed
EN_ADC
sys_div1
11
DESCRIPTION
0
3
0
2
S-bus output block and the clock to the ADC
2
S-bus input block and the interpolator
EN_DEC
sys_div0
10
1
2
0
s
clock and the clock of the
EN_DAC
s
PLL1
clock to the analog
Product specification
s
9
0
1
1
clock to the
s
clock to the
UDA1380
EN_INT
PLL0
8
1
0
0