IS42S16100A1-7T ISSI, Integrated Silicon Solution Inc, IS42S16100A1-7T Datasheet - Page 27

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IS42S16100A1-7T

Manufacturer Part Number
IS42S16100A1-7T
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S16100A1-7T

Organization
1Mx16
Density
16Mb
Address Bus
12b
Access Time (max)
6/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
50
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S16100A1-7T
Manufacturer:
ISSI
Quantity:
503
Part Number:
IS42S16100A1-7TL
Manufacturer:
ISSI
Quantity:
16
IS42S16100A1
Interval Between Read Command
A new command can be executed while a read cycle is in
progress, i.e., before that cycle completes. When the
second read command is executed, after the CAS latency
has elapsed, data corresponding to the new read command
is output in place of the data due to the previous read
command.
CAS latency = 2, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
08/12/03
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding to
the new write command can be input in place of the data
for the previous write command.
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
CLK
DQ
CLK
DQ
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
READ A0
WRITE A0 WRITE B0
D
IN
A0
READ B0
t
CCD
D
IN
t
CCD
B0
D
OUT
D
A0
IN
1-800-379-4774
B1
D
OUT
The interval between two write commands (t
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
The interval between two read command (t
least one clock cycle.
The selected bank must be set to the active state before
executing this command.
D
B0
IN
B2
D
OUT
D
B1
IN
B3
D
OUT
B2
D
OUT
B3
ISSI
CCD
CCD
) must be at
) must be
27
®

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