PPC440GX-3NF533C Applied Micro Circuits Corporation, PPC440GX-3NF533C Datasheet - Page 14

• Manufacturer Part Number: PPC440GX-3NF533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF533C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

440GX – Power PC 440GX Embedded Processor
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Universal Interrupt Controller (UIC)
Four Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include:
PLB Performance Monitor
The PLB Performance Monitor (PPM) provides hardware for counting certain events associated with PLB
transactions. The contents of the counters can be read by software for analysis and enhancement of PLB
performance, or software debug. The data includes identification and duration of the events.
I2O Messaging Unit (IMU)
The IMU interfaces to the PLB as a master or slave and allows messages to be transferred between two PLB
masters (for example, the 440 CPU and PCI-X).
Features include:
JTAG
Features include:
• 18 external interrupts
• 63 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
• Three messaging methods
• Up to 7 different interrupt outputs generated
• Support for interrupt masking
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)
- 4 Message registers—2 inbound, 2 outbound
- 2 Doorbell registers—1 inbound, 1 outbound
- 4 Circular queues—2 inbound, 2 outbound
Revision 1.20 – June 9, 2009
Data Sheet
AMCC