MC68HC711K4CFN3 Freescale Semiconductor, MC68HC711K4CFN3 Datasheet - Page 53
MC68HC711K4CFN3
Manufacturer Part Number
MC68HC711K4CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711K4CFN3.pdf
(290 pages)
Specifications of MC68HC711K4CFN3
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROM
Program Memory Size
24KB
Total Internal Ram Size
768Byte
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711K4CFN3
Manufacturer:
MOLEX
Quantity:
12 000
Part Number:
MC68HC711K4CFN3
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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3.5 Opcodes and Operands
3.6 Addressing Modes
M68HC11K Family
MOTOROLA
there are no special requirements for alignment of instructions or
operands.
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Every
instruction requires a unique opcode for each of its addressing modes.
The resulting number of opcodes exceeds the 256 available in an 8-bit
binary number. A 4-page opcode map has been implemented to
accommodate the extra instructions. An additional byte, called a
prebyte, directs the processor from page 0 of the opcode map to one of
the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero
to three operands. The operands contain information the CPU needs for
executing the instruction. Complete instructions can be from one to five
bytes long.
Six addressing modes can be used to access memory:
All modes except inherent mode use an effective address. The effective
address is the memory address where the argument is fetched or stored
or the address from which execution is to proceed. The effective address
can be specified within an instruction or it can be calculated.
1. Immediate
2. Direct
3. Extended
4. Indexed
5. Inherent
6. Relative
Freescale Semiconductor, Inc.
For More Information On This Product,
Central Processor Unit (CPU)
Go to: www.freescale.com
Central Processor Unit (CPU)
Opcodes and Operands
Technical Data
53
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