AM7969-175JC AMD (ADVANCED MICRO DEVICES), AM7969-175JC Datasheet - Page 62

• Manufacturer Part Number: AM7969-175JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM7969-175JC

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / Rohs Status: Not Compliant

Figure 3-1
58
AMD
This optimization is at the expense of lock-up time. In TAXI systems, lock-up time is
relatively unimportant, since the system must achieve lock only during system power-up.
If the PLL achieves proper lock within a few tens, or even hundreds of microseconds, its
startup will be similar to the start-up characteristics of the system power supply.
The actual time to lock begins during power-up, when both Transmitter and Receiver
are marginally powered and the entire link is marginally functional. Transient effects
other than PLL characteristics, which typically occur during power-up, can either
lengthen or shorten the apparent lock time. These effects are a function of actual
implementation and are not discussed here. The discussion which follows assumes that
both Transmitter and Receiver are fully powered, and that the link is fully operational.
The only effects included are PLL transient effects.
If there is no data on the link (if the Transmitter is off, or if there is a quiet line) the data
recovery PLL will drift to its natural oscillation frequency. This frequency is determined
by component values and tolerances inside the Am7969 receive PLL, and will vary
slightly from both the Receiver reference frequency (at X1 of the Receiver) and the
Transmitter data frequency (X1 of the Transmitter).
When data appears on the line, the receive PLL must achieve phase lock from its
resting frequency. The structure of the PLL used in the TAXIchip set ensures that this
resting frequency will be no more than a few percent (typically less than 3%) from the
reference frequency applied at X1. This is in addition to the specified Transmitter/Re-
ceiver frequency mismatch allowed by the crystal tolerance specification of +0.1%.
Calculated Receiver Lock-Up Time
Neglecting frequency variations in the Transmitter and jitter in the data stream, the time
to lock is related to the PLL loop bandwidth and damping factor, and to the transition
density. The loop parameters are set by the internal component values and tolerance of
the TAXIchip set. A plot of calculated lock-up time vs Transmitter to Receiver frequency
offset and transition density is given in the Figure 3-1. Note that low transition density
causes longer lock times. In fact, at very low transition densities (1 transition per 10 bit
times of the HQ symbol), and large offset frequencies, the PLL may not be able to
acquire lock at all, even though the lock equation used to produce the graph seems to
indicate a solution. As the limits are approached, lock time may grow to several times
the value predicted by the lock equation.
Lock-Up Time
( s)
80
70
60
50
40
30
20
10
0
TAXIchip Integrated Circuits Technical Manual
Percent Offset Frequency at 125 MHz
0.1
1
2
12330E-4
HQ
JK
II