P89C54X2BA NXP Semiconductors, P89C54X2BA Datasheet - Page 32

• Manufacturer Part Number: P89C54X2BA
• Manufacturer: NXP Semiconductors

Specifications of P89C54X2BA

• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
2002 Jun 06
80C51 8-bit Flash microcontroller family
4K/8K/16K/32K Flash
IPH
IP
IE
BIT
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
BIT
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
Address = B7H
Bit Addressable
Address = 0B8H
Bit Addressable
Address = 0A8H
Bit Addressable
SYMBOL
EA
—
ET2
ES
ET1
EX1
ET0
EX0
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
SYMBOL
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
EA
—
—
7
7
7
—
—
—
6
6
6
Figure 24. Interrupt Priority HIGH (IPH) Register
Figure 23. Interrupt Priority (IP) Register
Figure 22. Interrupt Enable (IE) Register
PT2H
ET2
PT2
5
5
5
PSH
ES
PS
4
4
4
32
PT1H
ET1
PT1
3
3
3
PX1H
EX1
PX1
2
2
2
PT0H
P89C51X2/52X2/54X2/58X2
ET0
PT0
1
1
1
SU01523
PX0H
EX0
PX0
0
0
0
SU01524
Reset Value = xx000000B
Reset Value = xx000000B
Reset Value = 0X000000B
SU01522
Preliminary data