SAB80C535N Infineon Technologies, SAB80C535N Datasheet - Page 35

• Manufacturer Part Number: SAB80C535N
• Manufacturer: Infineon Technologies

Specifications of SAB80C535N

• Cpu Family: C500
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: Serial
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 48
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note that PCON is not a bit-addressable register, so the above mentioned sequence for
entering the power-down mode is obtained by byte-handling instructions, as shown in the
following example:
ORL
ORL
The instruction that sets bit PDS is the last instruction executed before going into
power-down mode.
The only exit from power-down mode is a hardware reset. Reset will redefine all SFR's, but will
not change the contents of the internal RAM.
In the power-down mode of operation, V
must be ensured, however, that V
and that V
terminated. The reset signal that terminates the power-down mode also restarts the oscillator.
The reset should not be activated before V
be held active long enough to allow the oscillator to restart and stabilize (similar to power-on
reset).
Differences in Pin Assignments of the SAB 80C515 and SAB 80515
Since the SAB 80C515 is designed in CMOS technology, this device requires no V
cause the die's substrate is internally connected to V
Furthermore, the RAM backup power supply via pin V
power-down mode and power supply via V
Therefore, pins V
the SAB 80C515.
Pin 4 (the former pin V
Pin 37 (the former pin V
decoupling capacitor between pin 37 (V
avoiding long wiring and reducing the voltage distortion resulting from high dynamic current
peaks.
There is a difference between the NMOS and CMOS version concerning the clock circuitry.
When the device is driven from an external source, pin XTAL2 must be driven by the clock
signal; pin XTAL1, however, must be left open in the SAB 80C515 (must be tied low in the
NMOS version). When using the oscillator with a crystal there is no difference in the circuitry.
Thus, due to its pin compatibility the SAB 80C515 normally substitutes any SAB 80515 without
redesign of the user’s printed circuit board, but the user has to take care that the two V
are hardwired on-chip. In any case, it is recommended that power is supplied on both V
of the SAB 80C515 to improve the power supply to the chip.
If the power saving modes are to be used, pin PE must be tied low, otherwise these modes are
disabled.
Semiconductor Group
PCON,#00000010
PCON,#01000000
CC
is restored to its normal operating level, before the power-down mode is
B B
and V
PD
BB
) is the new PE pin which enables the use of the power saving modes.
) becomes an additional V
PD
B
B
of the NMOS version SAB 80515 are used for other functions in
;Set bit PDE, bit PDS must not be set
;Set bit PDS, bit PDE must not be set
CC
is not reduced before the power- down mode is invoked,
CC
CC
CC
) and pin 38 (V
CC
can be reduced to minimize power consumption. It
34
.
is restored to its normal operating level and must
CC
CC
PD
.
pin. Thus, it is possible to insert a
is replaced by the software- controlled
SS
) very close to the device, thereby
SAB 80C515/80C535
B B
CC
CC
pin, be-
pins
pins