DT28F160F3T95 Intel, DT28F160F3T95 Datasheet - Page 24
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DT28F160F3T95
Manufacturer Part Number
DT28F160F3T95
Description
Manufacturer
Intel
Datasheet
1.DT28F160F3T95.pdf
(48 pages)
Specifications of DT28F160F3T95
Density
16Mb
Access Time (max)
95ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
SSOP
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
1M
Supply Current
60mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DT28F160F3T95
Manufacturer:
INTEL
Quantity:
147
28F800F3—Automotive
4.9.4
4.9.5
4.9.6
18
Starting
(Dec.)
Addr.
Figure 6. Output Configuration
Table 8.
15
0
1
3
3
4
5
6
7
8
9
4-Word Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Linear
Wait # Configuration – (RCR.8)
The WAIT# configuration bit controls the behavior of the WAIT# output signal. This output signal
can be set to be asserted during or one CLK cycle before an output delay when continuous burst
length is enabled. Its setting will depend on the system and CPU characteristic.
Burst Sequence – (RCR.7)
The burst sequence specifies the order in which data is addressed in synchronous burst mode. This
order is programmable as either linear or Intel burst order. The continuous burst length only
supports linear burst order. The order chosen will depend on the CPU characteristic. See
for more details.
Sequence and Burst Length
Clock Configuration – (RCR.6)
The clock configuration configures the device to start a burst cycle, output data, and assert WAIT#
on the rising or falling edge of the clock. CLK flexibility helps ease 3 Volt Fast Boot Block Flash
memory interface to a wide range of burst CPUs.
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Intel
Data Hold
Data hold
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
1 CLK
2 CLK
Burst Addressing Sequence (Dec.)
Linear
DQ
DQ
8-Word Burst Length
15-0
15-0
CLK (C)
(D/Q)
(D/Q)
Output
Valid
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
Output
Valid
Intel
NA
NA
NA
Output
Valid
Output
Valid
15-16-17-18-19-20-21-...
8-9-10-11-12-13-14-...
7-8-9-10-11-12-13-...
6-7-8-9-10-11-12-...
Continuous Burst
5-6-7-8-9-10-11-...
4-5-6-7-8-9-10-..
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-...
PRELIMINARY
Linear
...
Table 8