PCA9544D NXP Semiconductors, PCA9544D Datasheet - Page 8

• Manufacturer Part Number: PCA9544D
• Manufacturer: NXP Semiconductors

Specifications of PCA9544D

• Logical Function: I2C Multiplexer
• Configuration: 1 x 4:1
• Number Of Inputs: 4
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Power Dissipation: 400mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SO
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
2004 Sep 29
4-channel I
BY TRANSMITTER
SDA
DATA OUTPUT
2
DATA OUTPUT
BY RECEIVER
C multiplexer with interrupt logic
SCL FROM
start condition
SDA
MASTER
S
1
start condition
S
START condition
1
1
SLAVE ADDRESS
1
S
1
0
SLAVE ADDRESS
1
A2
Figure 10. Acknowledgement on the I
0
A1 A0
A2
Figure 11. WRITE control register
Figure 12. READ control register
1
A1
R/W
0
A0
A
R/W
acknowledge
from slave
1
X
2
A
acknowledge
from slave
CONTROL REGISTER
8
INT3
X
X
INT2
CONTROL REGISTER
not acknowledge
X
INT1
acknowledge
X
INT0
8
B2
2
X
C-bus
acknowledge
from slave
B1
B2
no acknowledge
from master
B0
B1
9
A
B0
last byte
P
NA
P
stop condition
clock pulse for
acknowledgement
SW00378
SW00802
PCA9544
Product data sheet
SW00368