ICS8735AM-21 IDT, Integrated Device Technology Inc, ICS8735AM-21 Datasheet - Page 2

• Manufacturer Part Number: ICS8735AM-21
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay PLL Clock Generatorr

Specifications of ICS8735AM-21

• Number Of Elements: 1
• Supply Current: 150mA
• Pll Input Freq (min): 31.25MHz
• Pll Input Freq (max): 700MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOIC
• Output Frequency Range: Up to 700MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Symbol
C
R
R
SEL0, SEL1,
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
SEL2, SEL3
nQFB, QFB
IN
PULLUP
PULLDOWN
PLL_SEL
nFB_IN
FB_IN
Name
nQ, Q
nCLK
V
V
CLK
V
V
MR
CCO
CCA
CC
EE
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Inverting differential clock input.
Inverting differential feedback input to phase detector for regenerating clocks with “zero delay.”
Description
Non-inverting differential clock input.
Non-inverted differential feedback input to phase detector for regenerating clocks with
“zero delay.”
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true
output Q to go low and the inverted output nQ to go high. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
PLL select. Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential feedback output pair. LVPECL interface levels.
Negative supply pin.
Core supply pins.
Analog supply pin.
Output supply pin.
Test Conditions
2
Minimum
ICS8735AM-21 REV. A JULY 31, 2008
Typical
51
51
4
Maximum
Units
k
k
pF
Ω
Ω