LT5537EDDB#PBF Linear Technology, LT5537EDDB#PBF Datasheet - Page 13

• Manufacturer Part Number: LT5537EDDB#PBF
• Manufacturer: Linear Technology

Specifications of LT5537EDDB#PBF

• Pin Count: 8
• Screening Level: Industrial
• Package Type: DFN
• Lead Free Status / Rohs Status: Compliant

APPLICATIO S I FOR ATIO
Design 2 is the application circuit (Figure 13) used for
characterization in this data sheet. This is a robust general
purpose design which can operate as low as 1.3MHz.
Optional filter capacitor (C6 = 33nF) together with the on-
chip capacitor set the dominant pole at 740Hz. The input
pole associated with the AC coupling capacitors (C1, C2 =
100pF) is at 1.3MHz which is beyond the loop cut-off
frequency of 160kHz. The zero is at an even higher
frequency and can be safely ignored. This design has a
stability phase margin of 84 degrees, resulting in a very
well damped response to any input biasing transients.
Design 3 features fast settling. This design is appropriate
when fast response in the presence of input biasing
transients is required, and very low frequency operation is
not needed.
Design 4 demonstrates the possibility of operating the
LT5537 at very low frequency (<10kHz) by configuring the
offset cancellation loop for very low bandwidth. The re-
sponse of this circuit at 10kHz is plotted in Figure 11.
2.5
2.0
1.5
1.0
0.5
0
–100
T
V
A
CC
= 25°C
Figure 11. 10kHz Operation
= ENBL = 3V
–80
U
INPUT POWER (dBm)
–60
U
–40
–20
W
0
5537 F17
20
U
Offset Cancellation Loop and the Timing Response
The input of the LT5537 is AC coupled, and the on-chip DC
biasing is automatically regulated as described above. But
if the DC component of the input signal has any transient
step with sufficiently short rise or fall time (for example the
output of an active RF switch has a biasing shift between
switching states), a transient voltage pulse is induced by
the displacement current needed to charge the input AC
coupling capacitor. Also, if the pulse frequency or the
repetition rate is within the loop bandwidth of the offset
cancellation circuit, the LT5537 will respond to the in-
duced voltage pulse in the same way it nulls out its internal
DC offset, even though the chip is DC isolated from the
input signal.
If the external capacitor (C6) is used to extend the low
frequency response of the LT5537, then this will also
lengthen the response time of the DC offset cancellation
circuit. In the presence of DC steps or glitches at the input,
the transient response of the slowed offset cancellation
loop will be superimposed on the faster logarithmic detec-
tor output, degrading the overall response time of the chip.
The sensitivity of the LT5537 is very high. An input biasing
step with amplitude of 0.5mV can generate a output
voltage response of 400mV before the input voltage tran-
sient dissipates or the offset cancellation loop nulls out the
transient, whichever occurs first.
One way to prevent the input signal containing a biasing
transient from degrading the timing response is to design
the offset cancellation loop to have a high bandwidth,
allowing faster settling. Design 3 in Table 3 is suitable for
this purpose, but will not operate below 20MHz.
LT5537
13
5537fa