WJCE6353 S L9G5 Intel, WJCE6353 S L9G5 Datasheet - Page 18

• Manufacturer Part Number: WJCE6353 S L9G5
• Manufacturer: Intel

Specifications of WJCE6353 S L9G5

• Pin Count: 64
• Screening Level: Commercial
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

Data Sheet
3.2.2
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in the packet
synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running clock once symbol
lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 8 with MOCLKINV = ‘1’, the default
state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK (MOCLKINV = 1)
to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during the
inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of a packet
and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet where uncor-
rectable bytes are detected and will remain low until the last byte has been clocked out.
Figure 8 - MPEG Output Data Waveforms
3.2.3
Maximum delay conditions: Vdd = 3.0V, CVdd = 1.62V, Tamb = 80
Minimum delay conditions: Vdd = 3.6V, CVdd = 1.98V, Tamb = -10
MOCLK frequency = 45.06 MHz.
3.2.4
18
Data output delay t
Setup Time t
Hold Time t
Parameter
MPEG Data Output Signals
MPEG Output Timing
MOCLKINV
H
MOCLKINV=1
MOCLK
MDO7:0
MOSTRT
MOVAL
BKERR
SU
D
=
1
1st byte packet n
Maximum
3.0
7.0
7.0
Delay conditions
Minimum
10.0
10.0
1.0
Tp
188 byte packet n
Intel Corporation
Units
CE6353
ns
o
o
C, Output load = 10pF.
C, Output load = 10pF.
Ti
1st byte packet n+1