TDA8751 NXP Semiconductors, TDA8751 Datasheet - Page 5

• Manufacturer Part Number: TDA8751
• Manufacturer: NXP Semiconductors

Specifications of TDA8751

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The QPSK modulated signal is applied to the input as an
asymmetrical RF signal in the bandwidth 44 to 130 MHz.
The spectrum extension to this waveform must be limited
by a band-pass filter superseding the IC.
The RF input is either the LNA input, if the level is
mixed with two clocks in quadrature to provide the
base-band demodulated In-phase (I) and Quad-phase (Q)
signals.
The VCO operates at twice the RF carrier frequency in the
bandwidth 88 - 260 MHz (one octave), therefore the
0 to 90 clocks are generated by a divider by 2.
The VCO frequency can be programmed by an integrated
PLL that tunes the external LC tank circuit.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
HANDLING
HBM ESD: The IC pins withstand 2 kV except pin 26 (1750 V).
MM ESD: The IC pins withstand 100 V except pins 2 and 31 (75 V).
THERMAL CHARACTERISTICS
1999 Aug 20
V
V
t
T
T
T
V
R
30 to 0 dBmVrms, or the DEMOD input if the level is
20 to +10 dBmVrms. The amplified RF signal is then
sc
SYMBOL
stg
j(max)
amb
SYMBOL
CC
(max)
CC(tune)
th(j-a)
QPSK receiver
supply voltage
maximum voltage on all pins except pin 9 (5 V)
maximum short circuit duration on outputs
storage temperature
maximum junction temperature
operating ambient temperature
tuning voltage supply
thermal resistance from junction to ambient
PARAMETER
PARAMETER
5
The raw I and Q generated signals contain spurious
spikes, therefore each signal is passed through a third
order active low-pass filter (RC cell + Sallen-Key
structure), whose cut-off frequency is set by external
components. The filtered I and Q data signals are then
amplified to provide balanced buffer outputs.
The data sent to the PLL is loaded in bursts, framed by
signal EN. Programming clock edges, together with their
relevant data bits, are ignored until EN becomes active
(LOW). The internal latches are updated with the latest
programming data when EN returns to inactive (HIGH).
The last 14 bits only are retained within the programming
register. No check is made on the number of clock pulses
received while programming is enabled. An active clock
edge causing a shift of the data bits is generated when
EN goes HIGH while CLOCK is still LOW. The main divider
ratio and the reference divider ratio are provided via the
serial bus (see Table 1).
in free air
CONDITIONS
0
0.3
0.3
40
0.3
MIN.
VALUE
65
6.0
V
10
+150
150
70
30
Product specification
CC
MAX.
TDA8051
V
V
s
V
UNIT
K/W
C
C
C
UNIT