T5760NTGS Atmel, T5760NTGS Datasheet - Page 17

• Manufacturer Part Number: T5760NTGS
• Manufacturer: Atmel

Specifications of T5760NTGS

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

9. Data Clock
9.1
4561C–RKE–05/05
Generation of the Data Clock
Figure 8-11 on page 16
ING/_ON. The pin POLLING/_ON must be held to low for the time period t
edge on pin POLLING/_ON and the delay t
T
This command is faster than using pin DATA at the cost of an additional connection to the
microcontroller.
Figure 8-12 on page 16
POLLING/_ON. The pin POLLING/_ON must be held to Low. After the delay t
changes from sleep mode to start-up mode regardless the programmed values for T
N
ignored, but not deleted (see section
If the receiver is polled exclusively by a microcontroller, T
manent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON
is held to High.
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift reg-
ister. Using this data clock, a microcontroller can easily synchronize the data stream. This clock
can only be used for Manchester and Bi-phase coded signals.
After a successful bit check, the receiver switches from polling mode to receiving mode and the
data stream is available at pin DATA. In receiving mode, the data clock control logic (Manches-
ter/Bi-phase demodulator) is active and examines the incoming data stream. This is done, like in
the bit check, by subsequent time frame checks where the distance between two edges is con-
tinuously compared to a programmable time window. As illustrated in
only two distances between two edges in Manchester and Bi-phase coded signals are valid (T
and 2T).
The limits for T are the same as used for the bit check. They can be programmed in the LIMIT-
register (Lim_min and Lim_max, see
The limits for 2T are calculated as follows:
Lower limit of 2T:
Upper limit of 2T:
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it will be round up)
The data clock is available, after the data clock control logic has detected the distance 2T (Start
bit) and is issued with the delay t
If the data clock control logic detects a timing or logical error (Manchester code violation), like
illustrated in
clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again with the
generation of the data clock (see
Sleep
Bit-check
elapses.
. As long as POLLING/_ON is held to Low, the values for T
Figure 9-2 on page 18
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
illustrates how to set the receiver back to polling mode via pin POLL-
illustrates how to set the receiver to receiving mode via the pin
Delay
Figure 9-4 on page
and
“Digital Noise Suppression” on page
Table 11-10 on page 25
after the edge on pin DATA (see
Figure 9-3 on page
on3
, the polling mode is active and the sleep time
19).
Sleep
19, it stops the output of the data
and
must be programmed to 31 (per-
Table 11-11 on page
Sleep
Figure 9-1 on page
T5760/T5761
Figure 9-1 on page
20).
on2
and N
. After the positive
on1
Bit-check
, the receiver
Sleep
25).
will be
18).
and
18,
17