TEA5777HN/N2 STEricsson, TEA5777HN/N2 Datasheet - Page 17

• Manufacturer Part Number: TEA5777HN/N2
• Manufacturer: STEricsson

Specifications of TEA5777HN/N2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
TEA5777_1
Product data sheet
9.3.1 Write mode
9.3 I
The I
In the I
pin WRITE_READ is don’t care.
Data transfer to the bus interface is byte oriented and no sub-addressing is used.
The data transfer consists of a START condition, device address byte plus R/W
Data is written at the rising edge and data is clocked out at the falling edge. The I
can operate at a maximum clock frequency of 400 kHz.
The I
Table 4.
The bus interface has a total of 6 write registers. Before data can be written to these
registers, the I
After the bus interface (slave) recognizes a start of transmission, the address byte is
written to the bus. If the address is equal to the internal address of the bus interface, an
acknowledge is given to the master and data can be written to the write registers.
If the bus address does not match, no acknowledge is given and the internal bus interface
clock is disabled until a next start is detected.
Condition
START
ACK
ACK
ACK
ACK
STOP
2
C-bus mode
2
2
C-bus interface is based on ‘The I
C-bus device address of the TEA5777 is: 110 0000 (7 bits).
2
C-bus mode, only pins CLOCK and DATA are used for data transfer. The level on
I
2
C-bus data transfer
2
C-bus device address byte has to be written to the IC
Byte
Address byte
Byte 1
Byte 2
Byte n
Rev. 01 — 11 April 2006
Low-power AM/FM stereo radio for handheld applications
Description
start by master
device address + R/W bit
acknowledge by slave
data byte 1
acknowledge by slave
data byte 2
acknowledge by slave
data byte n
acknowledge by slave
stop by master
2
C-bus specification’ version 2.1 January 2000.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
TEA5777
2
C-bus
16 of 47