M95320-WMN6 STMicroelectronics, M95320-WMN6 Datasheet - Page 19

• Manufacturer Part Number: M95320-WMN6
• Description: EEPROM 5.5V 32K (4Kx8)
• Manufacturer: STMicroelectronics

Specifications of M95320-WMN6

• Memory Size: 32 Kbit
• Organization: 4 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 5 MHz
• Access Time: 60 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-8
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Operating Temperature: - 40 C to + 85 C
• Lead Free Status / Rohs Status: No

M95320, M95320-W, M95320-R
6.4
Figure 9.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
sending the instruction code followed by the data byte on Serial Data input (D), and driving
the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of
Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not
executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes t
Table
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
reset at the end of the write cycle t
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
●
●
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register. Bits b6, b5, b4 are always read as 0.
The Block protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in
The SRWD bit (Status register write disable bit), in accordance with the signal read on
the Write protect pin (W), allows the user to set or reset the write protection mode of the
Status Register itself, as shown in
Write Status Register (WRSR) instruction is not executed.
20). The instruction sequence is shown in
W
, and is 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
S
C
D
Q
Read Status Register (RDSR) sequence
0
High Impedance
1
2
Instruction
3 4 5 6 7 8 9 10 11 12 13 14 15
W
Table
Doc ID 5711 Rev 12
to complete (as specified in
W
W
2.
write cycle.
.
MSB
7 6 5 4 3 2 1 0
Table
Status Register Out
5. When in the Write-protected mode, the
Figure
10.
MSB
7 6 5 4 3 2 1 0
Table
Status Register Out
17,
Table
18,
7
AI02031E
Table
Instructions
19,
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