M29DW324DB70N6 STMicroelectronics, M29DW324DB70N6 Datasheet - Page 13

• Manufacturer Part Number: M29DW324DB70N6
• Description: Flash 32M (4Mx8 or 2Mx16)
• Manufacturer: STMicroelectronics

Specifications of M29DW324DB70N6

• Data Bus Width: 8 bit, 16 bit
• Memory Type: NOR Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: CFI
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 10 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-48
• Organization: 4 MB x 8
• Lead Free Status / Rohs Status: No

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29DW324D
allows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 12, Read Mode AC Waveforms,
and Table 13, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 14 and 15, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
IH
IH
.
. The Data Inputs/Outputs will output the
IH
, during the whole Bus
IL
, to Chip Enable
IH
, the
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 12, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and Chip Unprotect. Groups
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in Appendix A, Tables 21 and 22, Block Address-
es. The whole chip can be unprotected to allow the
data inside the blocks to be changed.
The V
the two outermost boot blocks. When V
Protect is at V
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in Appendix D.
PP
/Write Protect pin can be used to protect
CC3
, for Program or Erase operations un-
IL
M29DW324DT, M29DW324DB
ID
CC
the two outermost boot blocks are
to be applied to some pins.
± 0.2V. For the Standby current
CC2
, Chip Enable should
CC
CC2
PP
± 0.2V)
/Write
. The
13/49
of