ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 152

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.4
12.4.1
12.4.2
12.4.3
12.4.3.1
12.4.3.2
12.5
12.5.1
12.5.2
13
13.1
13.2
13.3
13.4
13.5
13.6
14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.4
14.4.1
14.4.2
14.4.3
14.4.4
ISP1362_5
Product data sheet
OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Host Controller registers. . . . . . . . . . . . . . . . . 68
Endpoint description . . . . . . . . . . . . . . . . . . . . 52
Endpoints with programmable buffer memory
size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 52
Endpoint buffer memory size . . . . . . . . . . . . . 52
Endpoint initialization . . . . . . . . . . . . . . . . . . . 53
Endpoint I/O mode access . . . . . . . . . . . . . . . 54
Special actions on control endpoints . . . . . . . 54
Peripheral Controller DMA transfer . . . . . . . . . 54
Selecting an endpoint for the DMA transfer . . 55
8237 compatible mode . . . . . . . . . . . . . . . . . . 55
End-Of-Transfer conditions . . . . . . . . . . . . . . . 57
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 57
Isochronous endpoints . . . . . . . . . . . . . . . . . . 58
ISP1362 Peripheral Controller suspend and
resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Suspend conditions . . . . . . . . . . . . . . . . . . . . 58
Resume conditions . . . . . . . . . . . . . . . . . . . . . 59
OtgControl register (R/W: 62h/E2h) . . . . . . . . 60
OtgStatus register (R: 67h). . . . . . . . . . . . . . . 62
OtgInterrupt register (R/W: 68h/E8h) . . . . . . . 63
OtgInterruptEnable register (R/W: 69h/E9h). . 65
OtgTimer register (R/W: 6Ah/EAh) . . . . . . . . . 66
OtgAltTimer register (R/W: 6Ch/ECh). . . . . . . 67
HC control and status registers . . . . . . . . . . . 70
HcRevision register (R: 00h). . . . . . . . . . . . . . 70
HcControl register (R/W: 01h/81h) . . . . . . . . . 70
HcCommandStatus register (R/W: 02h/82h) . 72
HcInterruptStatus register (R/W: 03h/83h) . . . 73
HcInterruptEnable register (R/W: 04h/84h) . . 74
HcInterruptDisable register (R/W: 05h/85h) . . 75
HC frame counter registers. . . . . . . . . . . . . . . 76
HcFmInterval register (R/W: 0Dh/8Dh). . . . . . 76
HcFmRemaining register (R/W: 0Eh/8Eh) . . . 77
HcFmNumber register (R/W: 0Fh/8Fh). . . . . . 78
HcLSThreshold register (R/W: 11h/91h). . . . . 79
HC root hub registers . . . . . . . . . . . . . . . . . . . 80
HcRhDescriptorA register (R/W: 12h/92h) . . . 80
HcRhDescriptorB register (R/W: 13h/93h) . . . 82
HcRhStatus register (R/W: 14h/94h) . . . . . . . 83
HcRhPortStatus[1:2] register (R/W [1]:
15h/95h; [2]: 16h/96h). . . . . . . . . . . . . . . . . . . 84
HC DMA and interrupt control registers . . . . . 88
HcHardwareConfiguration register (R/W:
20h/A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
HcDMAConfiguration register (R/W: 21h/A1h) 90
HcTransferCounter register (R/W: 22h/A2h) . . 91
HcmPInterrupt register (R/W: 24h/A4h) . . . . . 91
Rev. 05 — 8 May 2007
14.4.5
14.5
14.5.1
14.5.2
14.5.3
14.6
14.6.1
14.6.2
14.6.3
14.7
14.7.1
14.7.2
14.7.3
14.7.4
14.8
14.8.1
14.8.2
14.8.3
14.8.4
14.8.5
14.8.6
14.8.7
14.9
14.9.1
14.9.2
14.9.3
14.9.4
14.9.5
14.9.6
14.9.7
14.9.8
14.9.9
15
15.1
15.1.1
15.1.2
15.1.3
15.1.4
15.1.5
15.1.6
15.1.7
15.1.8
15.2
Peripheral Controller registers. . . . . . . . . . . 106
HcmPInterruptEnable register (R/W: 25h/A5h) 93
HC miscellaneous registers . . . . . . . . . . . . . . 94
HcChipID register (R: 27h). . . . . . . . . . . . . . . 94
HcScratch register (R/W: 28h/A8h) . . . . . . . . 94
HcSoftwareReset register (W: A9h) . . . . . . . . 95
HC buffer RAM control registers . . . . . . . . . . 95
HcBufferStatus register (R/W: 2Ch/ACh) . . . . 95
HcDirectAddressLength register
(R/W: 32h/B2h) . . . . . . . . . . . . . . . . . . . . . . . 96
HcDirectAddressData register (R/W: 45h/C5h) 97
Isochronous (ISO) transfer registers . . . . . . . 97
HcISTLBufferSize register (R/W: 30h/B0h) . . 97
HcISTL0BufferPort register (R/W: 40h/C0h) . 97
HcISTL1BufferPort register (R/W: 42h/C2h) . 98
HcISTLToggleRate register (R/W: 47h/C7h) . 98
Interrupt transfer registers . . . . . . . . . . . . . . . 99
HcINTLBufferSize register (R/W: 33h/B3h) . . 99
HcINTLBufferPort register (R/W: 43h/C3h) . . 99
HcINTLBlkSize register (R/W: 53h/D3h) . . . 100
HcINTLPTDDoneMap register (R: 17h) . . . . 100
HcINTLPTDSkipMap register (R/W: 18h/98h) 100
HcINTLLastPTD register (R/W: 19h/99h). . . 101
HcINTLCurrentActivePTD register (R: 1Ah). 101
Control and bulk transfer
(aperiodic transfer) registers . . . . . . . . . . . . 102
HcATLBufferSize register (R/W: 34h/B4h) . . 102
HcATLBufferPort register (R/W: 44h/C4h) . . 102
HcATLBlkSize register (R/W: 54h/D4h) . . . . 102
HcATLPTDDoneMap register (R: 1Bh) . . . . 103
HcATLPTDSkipMap register (R/W: 1Ch/9Ch) 103
HcATLLastPTD register (R/W: 1Dh/9Dh) . . . 104
HcATLCurrentActivePTD register (R: 1Eh) . 104
HcATLPTDDoneThresholdCount register
(R/W: 51h/D1h) . . . . . . . . . . . . . . . . . . . . . . 105
HcATLPTDDoneThresholdTimeOut register
(R/W: 52h/D2h) . . . . . . . . . . . . . . . . . . . . . . 105
Initialization commands . . . . . . . . . . . . . . . . 108
DcEndpointConfiguration register (R/W:
30h to 3Fh/20h to 2Fh). . . . . . . . . . . . . . . . . 108
DcAddress register (R/W: B7h/B6h) . . . . . . 109
DcMode register (R/W: B9h/B8h). . . . . . . . . 109
DcHardwareConfiguration register (R/W:
BBh/BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DcInterruptEnable register (R/W: C3h/C2h). 111
DcDMAConfiguration (R/W: F1h/F0h) . . . . . 113
DcDMACounter register (R/W: F3h/F2h) . . . 114
Reset device (F6h) . . . . . . . . . . . . . . . . . . . . 114
Data flow commands . . . . . . . . . . . . . . . . . . 115
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
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